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參數(shù)資料
| 型號(hào)： | AD1891JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SamplePort Stereo Asynchronous Sample Rate Converters |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 416K |
| 代理商： | AD1891JP |
AD1890/AD1891–SPECIFICATIONS
T E ST CONDIT IONS UNLE SS OT HE RWISE NOT E D
Supply Voltage
Ambient T emperature
MCLK
Load Capacitance
+5.0
25
20
100
V
°
C
MHz
pF
All minimums and maximums tested except as noted.
PE RFORMANCE
(Guaranteed over 0
°
C
≤
T
A
≤
70
°
C, V
DD
= 5.0 V
±
10%, 8 MHz
≤
MCLK
≤
20 MHz)
Min
Max
Units
AD1890 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
AD1891 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
T otal Harmonic Distortion + Noise
AD1890 and AD1891 (20 Hz to 20 kHz, Full-Scale Input,
F
SOUT
/F
SIN
Between 0.5 and 2.0)
AD1890 (1 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)
AD1890 (10 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)
AD1891 (1 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)
AD1891 (10 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)
Interchannel Phase Deviation
Input and Output Sample Clock Jitter
(For
≤
1 dB Degradation in T HD+N with 10 kHz Full-Scale Input, Slow-Settling Mode)
120
96
dB
dB
dB
–94
–106
–100
–96
–95
0
dB
dB
dB
dB
dB
Degrees
ns
10
DIGIT AL INPUT S
(Guaranteed over 0
°
C
≤
T
A
≤
70
°
C, V
DD
= 5.0 V
±
10%, 8 MHz
≤
MCLK
≤
20 MHz)
Min
Max
Units
V
IH
V
IL
I
IH
@ V
IH
= +5 V
I
IL
@ V
IL
= 0 V
V
OH
@ I
OH
= –4 mA
V
OL
@ I
OL
= 4 mA
Input Capacitance
2.2
V
V
μ
A
μ
A
V
V
pF
0. 8
4
4
3.6
0.4
15
DIGIT AL T IMING
(Guaranteed over 0
°
C
≤
T
A
≤
70
°
C, V
DD
= 5.0 V
±
10%, 8 MHz
≤
MCLK
≤
20 MHz)
Min
Max
Units
t
MCLK
f
MCLK
t
MPWL
t
MPWH
f
LRI
t
RPWL
t
RS
t
BCLK
f
BCLK
t
BPWL
t
BPWH
t
WSI
t
WSO
t
LRSI
t
LRSO
t
DS
t
DH
t
DPD
t
DOH
MCLK Period
MCLK Frequency (1/t
MCLK
)
MCLK LO Pulse Width
MCLK HI Pulse Width
L
R
_I Frequency with 20 MHz MCLK
RESET
LO Pulse Width
RESET
Setup to MCLK Falling
BCLK _I/O Period
BCLK _I/O Frequency (l/t
BCLK
)
BCLK _I/O LO Pulse Width
BCLK _I/O HI Pulse Width
WCLK _I Setup to BCLK _I
WCLK _O Setup to BCLK _O
LR_I Setup to BCLK _I
LR_O Setup to BCLK _O
Data Setup to BCLK _I
Data Hold from BCLK _I
Data Propagation Delay from BCLK _O
Data Output Hold from BCLK _O
50
8
20
20
10
100
15
80
125
20
ns
MHz
ns
ns
kHz
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
12.5
40
40
15
30
15
30
0
25
40
5
REV. 0
–2–
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| AD1892 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital Receiver/Rate Converter |
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| AD1892JRRL | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
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| AD1893 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter |
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