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參數(shù)資料
| 型號： | AD1891JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SamplePort Stereo Asynchronous Sample Rate Converters |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 416K |
| 代理商： | AD1891JP |
AD1890/AD1891
REV. 0
–13–
appearance of the MSB of data is synchronous with the rising
edge of the left/
right
clock for the left channel and the falling
edge of left/
right
clock for the right channel. T he MSB is
delayed by one bit clock after the left/
right
clock if the MSB
delay mode is selected. T he word clock is not required in the
left/
right
clock triggered mode, and should be tied either HI or
LO. Figure 23 shows the bit clock in the optional gated or burst
mode; the bit clock is inactive between data fields, and can take
either the HI state or the LO state while inactive.
Note that there is no requirement for a delay between the left
channel data and the right channel data. T he left/
right
clocks
and the word clocks can transition immediately after the LSB of
the data, so that the MSB of the subsequent channel appears
without any timing delay. T he AD1891 is therefore capable of a
32-bit frame mode, in which both 16-bit channels are packed
into a 32-bit clock period. More generally, there is no particular
requirement for when the left/
right
clock falls (i.e., there is no
left/
right
clock duty cycle or pulse width specification), provided
that the left/
right
clock frequency equals the intended sample
frequency, and there are sufficient bit clock periods to clock in
or out the intended number of data bits.
Control Signals
T he GPDLYS, SET LSLW, BK POL_I, BK POL_O, T RGLR_I,
T RGLR_O, MSBDLY_I, and MSBDLY_O inputs are asyn-
chronous signals in that they need obey no particular timing
relation to MCLK or the sample clocks. Ordinarily, these pins
are hardwired or connected to an I/O register for microprocessor
control. T he only timing requirement on these pins is that the
control signals are stable and valid before the first serial input
data bit (i.e., the MSB) is presented to the AD1890/AD1891.
Reset
Figure 25 shows the reset timing for the AD1890/AD1891
SamplePorts. MCLK must be running when
RESET
is
asserted, and the bit clocks, the word clocks and the left/
right
clocks may also be running. When the AD1890/AD1891 come
out of reset, they default to a F
SIN
to F
SOUT
ratio of 1:1. T he fil-
ter pipeline is not cleared. However, the mute output goes HI
for at least 128 cycles, adequate to allow the pipeline to clear. If
F
SIN
differs significantly from F
SOUT
, then the AD1890/AD1891
sample clock servo control loop also has to settle. While settling,
the mute output will be HI. After the external system resets the
AD1890/AD1891, it should wait until the mute output goes LO
before clocking in serial data.
T here is no requirement for using the
RESET
pin at power-up
or when the input or output sample rate changes. If it is not
used, the AD1890/AD1891 will settle to the sample clocks sup-
plied within
≈
200 ms in fast-settling mode or within
≈
800 ms in
slow-settling mode.
OPE RAT ING FE AT URE S
Serial Input/Output Ports
T he AD1890/AD1891 use the frequency of the left/
right
input
clock (L
R
_I) and the left/
right
output clock (L
R
_O) signals to
determine the sample rate ratio, and therefore these signals must
run continuously and transition twice per sample period. (T he
L
R
_I clock frequency is equivalent to F
SIN
and the L
R
_O clock
frequency is equivalent to F
SOUT
.) T he other clocks (WCLK _I,
WCLK _O, BCLK _I, BCLK _O) are edge sensitive and may be
used in a gated or burst mode (i.e., a stream of pulses during
data transmission or reception followed by periods of inactivity).
T he word clocks and bit clocks are used only to write data into
or read data out of the serial ports; only the left/
right
clocks are
used in the internal DSP blocks. It is important that the left/
right
clocks are “clean” with monotonic rising and falling edge
transitions and no excessive overshoot or undershoot which
could cause false triggering on the AD1890/AD1891.
T he AD1890/AD1891’s flexible serial input and output ports
consume and produce data in twos-complement, MSB-first
format. T he left channel data field always precedes the right
channel data field; the current channel being consumed or pro-
duced is indicated by the state of the left/
right
clock (L
R
_I and
L
R
_O). A left channel field, right channel field pair is called a
frame. T he input data field consists of 4 to 20 bits for the
AD1890, and 4 to 16 bits for the AD1891. T he output data
field consists of 4 to 24 bits for both devices. T he input signals
are specified to T T L logic levels, and the outputs swing to full
CMOS logic levels. T he ports are configured by pin selections.
Serial I/O Port Modes
T he AD1890/AD1891 has pin-selectable bit clock polarity for
the input and output ports. In “normal” mode (BK POL_I or
BK POL_O LO) the data is valid on the rising edge. In the
“inverted” mode (BK POL_I or BK POL_O HI) the data is
valid on the falling edge. Both modes are shown in Figures 22
and 23.
In the pin selectable MSB delay mode, which can be set inde-
pendently for the input and output ports, the MSB is delayed by
one bit clock. T his is useful for I
2
S format compatibility and for
ease of interfacing to some DSP processors. Both the MSB de-
lay mode (MSBDLY_I or MSBDLY_O HI) and the MSB
non-delay mode (MSBDLY_I or MSBDLY_O LO) are shown
in Figures 22 and 23.
T he AD1890/AD1891 SamplePort serial ports operate in either
the word clock (WCLK _I, WCLK _O) triggered mode or left/
right
clock (L
R
_I, L
R
_O) triggered mode. T hese modes can be
utilized independently for the input and output ports, by reset-
ting or setting the T RGLR_I and T RGLR_O control lines
respectively. In the word clock triggered mode, as shown in Fig-
ure 22, after the left/
right
clock is valid, the appearance of the
MSB of data is synchronous with the rising edge of the word
clock (or delayed by one bit clock if the MSB delay mode is
selected). Note that the word clock is rising edge sensitive, and
can fall anytime after it is sampled HI by the bit clock. In the
left/
right
clock triggered mode, as shown in Figure 23, the
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