參數(shù)資料
型號(hào)： AD1818
廠商： Analog Devices, Inc.
英文描述： PCI SoundComm DC97 Digital Controller(PCI SoundComm DC97型數(shù)字控制器)
中文描述： 的PCI SoundComm DC97數(shù)字控制器（的PCI SoundComm DC97型數(shù)字控制器）
文件頁(yè)數(shù)： 21/29頁(yè)
文件大?。?/td> 364K
代理商： AD1818
AD1818
–21–
REV. 0
TECHNCAL
successive slots to slave codecs 1 or 2.
Bits 8 and 9 in the Analog Codec Interface Control Register are
used for test modes to control the SYNC and SDATA_OUT
pins. For normal operation they must be cleared.
DATA
Analog Codec Interface Control
There are several configurations in which the analog Codec
interface can work. These configurations are controlled by the
bits in the Analog Codec Interface Control/Status Register. Bits
in this register enable and reset the interface and control data
transfers to an AD1819 or other AC ’97 compatible codec. The
register can be accessed from the host through the PCI
interface and from the DSP. This register is shown below:
Analog Codec Interface Control/Status Register:
Bit 0
Analog Codec Interface Enable
Bit 1
Analog Codec Reset Disable
Bit 2
Audio Stream Output Enable
Bit 3
AD1819/AC ’97-Mode
Bit 5:4
AD1819 DSP Audio Output Control
Bit 6
AD1819 Modem I/O Enable
Bit 7
AD1819 Handset I/O Enable
Bit 8
Force SDATA_OUT High
Bit 9
Force SYNC High
Bit 15
Analog Codec Ready Status (RO)
The Codec Interface Enable (Bit 0) is the primary enable for
the AD1818 interface to the AC Link. Setting this bit will turn
on interface to use the external BIT_CLK signal coming in on
the link. Therefore, Bit 0 should be enabled after reset on
the AC Link has been disabled by setting Bit 1 in this register.
Turning on this bit will pull the RESET# pin high (inactive) on
the AC Link, thus enabling the BIT_CLK outputs on the
AC ’97 Codec.
Once the interface is out of reset and enabled, the codec should
be ready before any data or control words are sent to the codec.
The AD1818 monitors the Codec Ready status of the interface
and reflects it in Bit 15 of this register. This status signal is also
available to the DSP as flag input Bit 5. Codec ready going
high (active) signals that register transactions between the
AD1818 and the codec can occur.
Registers on the codec can be written and read by the host
through the PCI interface and by the DSP. The codec registers
are seen by the host at memory locations 0x1000 to 0x107F offset
from Base Address Register 0. These registers are accessible from
the DSP on I/O page 0x10, locations 0x00 to 0x7F.
Once the codec has been enabled and the mode of operation
set, data can begin to be sent to the interface. For standard
AC ’97 operation, the Audio Stream Output Enable should be
set and the AD1819/AC ’97-Mode bit left low. With the Audio
Stream Output Enable set, data from the Primary Summer
mixer output will be sent to the codec at a 48 kHz sample rate.
For extended functionality when using multiple AD1819
codecs, Bits 3 through 7 in the Analog Codec Interface Control
Register are used to control the system setup. With multiple
AD1819 codecs, AD1818 can be programmed to send six
channels of audio for Surround Sound (3 AD1819s), or two
audio channels plus modem data and handset channels (two
AD1819s), or other combinations.
Overall AD1819 operating modes are enabled by setting the
AD1819 mode (Bit 3) high. This enables all of the rest of the
control bits associated with the AD1819.
In AD1819 mode, there are two potential sources of audio data:
the Primary Summer mixer output or the DSP via FIFO #2.
Mixer output is enabled by setting the Audio Stream Output
Enable bit. If the DSP is to generate the audio data, then the
Audio Stream Output Enable bit should be low and the
AD1819 DSP Audio Output Control (Bits 5-4) used to control
the number of audio channels to be shipped to the AD1819s as
shown below:
Bits 5:4 # of 1819 DSP Audio Channels
00 No Audio Channels (Use Mixer If Enabled)
01 2 Audio Channels from DSP to AD1819
10 4 Audio Channels from DSP to AD1819
11 6 Audio Channels from DSP to AD1819
Bits 6 and 7 in the Analog Codec Interface Control Register
control the AD1819 Modem and Handset I/O Enables,
respectively. Modem and handset data generally is shipped to
and from the DSP to the codec interface. Control bits in the
DSP to Mixer FIFOs control which FIFOs send and receive the
modem and handset data.
When multiple AD1819s are used in a system with the AD1818,
there are requirements on the functionality performed by the
master AD1819. (See the AD1819 Data Sheet for more
information on codec master and slave organization.) When
mixer audio output is enabled, audio data is shipped on the first
two data channels in each frame, thus the master codec must be
on later channels, and thus the modem must be the slave codec.
When the DSP is used to supply audio data, however, the
modem data is shipped in the first two channels, therefore going
to the master codec. The DSP can ship two or four channels of
audio when modem is enabled. These channels will go in
相關(guān)PDF資料
PDF描述
AD1819A AC97 SoundPort Codec(AC97型聲音端口信號(hào)編解碼器)
AD1819BJST AC’97 SoundPort Codec
AD1819 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1819B AC’97 SoundPort Codec
AD1833A 24-Bit, 192 kHz, DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD18-182 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Non-Insulated; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:DISCONNECTFEMALE 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 21.08mm 5.84mm Tin
AD18-183 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Nylon; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:NON-INS FEM-187 DISC, 22-18 LEN .64 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 16.26mm 5.84mm Tin
AD1819 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec
AD1819AJST 制造商:Rochester Electronics LLC 功能描述:
AD1819B 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec
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