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參數(shù)資料
| 型號： | AD1818 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PCI SoundComm DC97 Digital Controller(PCI SoundComm DC97型數(shù)字控制器) |
| 中文描述： | 的PCI SoundComm DC97數(shù)字控制器（的PCI SoundComm DC97型數(shù)字控制器） |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 364K |
| 代理商： | AD1818 |
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AD1818
–14–
REV. 0
Scatter-Gather descriptors as needed by the audio synthesis
engine. When the End of Linked List (EOL) is reached, a
status bit will be set and the DMA will end if the sample is
not to be looped. If looping is to occur, DMA transfers will
continue from the beginning of the sample until a Stop
command is received in the Scatter-Gather command
register.
6. Bits in the Scatter-Gather command register control whether
or not an interrupt occurs when the End of Linked List is
reached or when the flag bit is set.
PCI Configuration Space Organization for the AD1818
The AD1818 contains a single Configuration Space with six
separate address spaces pointed to by address registers in that
configuration space. The function is logical device 0. All of the
AD1818 address spaces (including the Configuration Space) are
memory-mapped to the PCI bus.
TECHNCAL
DATA
DirectSound Output Channel to Select Channel Matching
Select
Data Stream
Transaction Source
Data Source
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DS[0]
DS[1]
DS[2]
DS[3]
DS[4]
DS[5]
DS[6]
DS[7]
Reserved
Reserved
dsp_out[0]
dsp_out[1]
Music Synth
var_out
audio out
hdsp_out
audio_in
modem_in
modem_out
mic_in
dsp_from[0]
dsp_from[1]
dsp_2_acif[0]
dsp_2_acif[1]
reserved
reserved
dsp_2_acif[2]
handset
music synth_in
Reserved
Reserved
Reserved
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter
Rate Converter
Rate Converter
Rate Converter
Rate Converter
Rate Converter
Rate Converter
Rate Converter
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/48 kHz
Rate Converter/Variable
Rate Converter/48 kHz
Rate Converter/48 kHz
AC ’97/48 kHz
AC ’97/Variable
AC ’97/Variable
AC ’97/Variable
Rate Converter/Variable
Rate Converter/Variable
AC ’97/Variable
AC ’97/Variable
Rate Converter
Rate Converter
Rate Converter
Rate Converter
Rate Converter
Rate Converter
AC ’97
AC ’97
AC ’97
DSP
DSP
DSP
DSP
AC ’97/Variable
AC ’97/ Variable
Rate Converter/22.05 kHz Music Synthesizer
DSP
DSP
PCI INTERFACE
In order to support the high data throughput required for
concurrent audio and telephony algorithms, the AD1818
includes a 33 MHz, 32-bit bus master 5 V PCI interface. The
interface is compliant with revision 2.1 of the PCI specification,
and the AD1818 is memory-mapped to the PCI bus.
THE AD1818 LOGICAL DEVICE
The DirectSound Mixer block provides the PCI interface necessary
for the 64-stream Mixer block. This interface supports the use
of system memory for storage of wavetable samples and envelopes.
On-chip FIFOs provide the buffering needed to support high
throughput on the PCI bus and samples as needed for the
wavetable synthesizer. Scatter-gather capability is provided for
each DMA channel. A MIDI MPU-401 interface to the MIDI
IN and MIDI OUT pins is also provided by this logical device.
The AC ’97 interface is the primary interface to the main analog
codec front-end. A FIFO buffers data to and from the serial
codec interface.
The PCI interface to the on-chip DSP provides both master and
slave burst capability between system memory and the on-chip
DSP memory. Separate target addressing is provided for the
24-bit DSP program memory space and the 16-bit DSP data
memory space. Bus master DMA can be controlled by either the
DSP through an internal interface or the host via the PCI inter-
face. Separate data FIFOs exist for target and master transfers.
SCATTER-GATHER DMA ON THE AD1818
When Direct Memory Access (DMA) is active, it will “steal”
one cycle from the DSP core for each transfer that takes place.
During the DMA transfer, no other DSP core activity occurs.
When transferring audio samples to the wavetable engine or the
codec engine, the DMA transfer can be programmed to perform
scatter-gather DMA. This mode allows the audio samples to be
split up in memory, and yet able to be transferred to and from
the AD1818 without processor intervention. In Scatter-Gather
mode, the DMA controller can read the memory address and
word count from an array of buffer descriptors called the
Scatter-Gather Descriptor (SGD) table. This allows the DMA
engine to sustain DMA transfers until all buffers in the Scatter-
Gather Descriptor table are transferred.
To initiate a Scatter-Gather transfer between memory and the
AD1818, the following steps are involved:
1. Software driver prepares a SGD table in system memory. Each
Scatter-Gather Descriptor (SGD) is eight bytes long and con-
sists of an address pointer to the starting address and the trans-
fer count of the memory buffer to be transferred. In any given
SGD table, two consecutive SGDs are offset by eight bytes and
are aligned on a 4-byte boundary. Each SGD contains:
a. Memory Address (Buffer Start) – 4 Bytes
b. Byte Count (Buffer Size) – 3 Bytes
c. End of Linked List (EOL) – 1 Bit (MSB)
d. Flag – 1 Bit
2. Initialize DMA control registers with transfer specific
information such as bit width, compression mode, etc.
table.
4. Engage Scatter-Gather DMA by writing the Start value to
the Scatter-Gather Command register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1819A | AC97 SoundPort Codec(AC97型聲音端口信號編解碼器) |
| AD1819BJST | AC’97 SoundPort Codec |
| AD1819 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1819B | AC’97 SoundPort Codec |
| AD1833A | 24-Bit, 192 kHz, DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD18-182 | 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Non-Insulated; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:DISCONNECTFEMALE 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 21.08mm 5.84mm Tin |
| AD18-183 | 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Nylon; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:NON-INS FEM-187 DISC, 22-18 LEN .64 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 16.26mm 5.84mm Tin |
| AD1819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec |
| AD1819AJST | 制造商:Rochester Electronics LLC 功能描述: |
| AD1819B | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec |
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