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參數(shù)資料
| 型號(hào)： | AD1818 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PCI SoundComm DC97 Digital Controller(PCI SoundComm DC97型數(shù)字控制器) |
| 中文描述： | 的PCI SoundComm DC97數(shù)字控制器（的PCI SoundComm DC97型數(shù)字控制器） |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 364K |
| 代理商： | AD1818 |
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AD1818
–20–
REV. 0
PRELMNARY
Bit (18:12) Control Register Index (Echo of register index
TECHNCAL
DATA
Bit (11:0)
The first bit (MSB) generated by the AC ’97 is always stuffed
with a 0. The following seven bit positions communicate the
associated control register address and the trailing 12 bit
positions are stuffed with 0s by the AC ’97.
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Status Data Port Bit Assignments:
Bit (19:4) Control Register Read Data (Stuffed with 0s if tagged
Command Address Port Bit Assignments:
Bit (19)
write/read command
Bit (18:12) Control Register Index (64 16-bit locations,
(1 = read, 0 = write)
addressed on even byte
boundaries)
(Stuffed with 1s)
Bit (11:0)
The first bit (MSB) sampled by the AC ’97 indicates whether
the current control transaction is a read or write operation. The
following seven-bit positions communicate the targeted control
register address. The trailing 12-bit positions within the slot are
reserved and are stuffed with 0s by the AD1818.
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register
write data in the event that the current command port operation
is a write cycle (as indicated by Slot 1 Bit 19).
Command Data Port Bit Assignments:
Bit (19:4) Control Register Write Data (Stuffed with 0s if cur-
Reserved
rent operation is a read)
(Stuffed with 0s)
Bit (3:0)
Slots 3–12: Data Input Channels
Slots 3 through 12 are data input channels assigned to audio or
modem streams as defined by the Analog Codec Interface Control/
Status Register in the AD1818. Each slot is defined as follows:
Data Output Bit Assignments:
Bit (19:4) Output Data
Reserved
(Stuffed with 0s if
current slot is invalid)
(Stuffed with 0s)
Bit (3:0)
AC Link Audio Input Stream (SDATA_IN)
The audio input frame data streams correspond to the multiplexed
bundles of all digital input data targeting the AD1818. As in the
case for the audio output stream, each AC Link audio input frame
consists of 12 20-bit time slots. Slot 0 is a special reserved time
slot containing 16 bits used for AC Link protocol infrastructure.
Within Slot 0, there is a global bit (SDATA_OUT Slot 0 Bit
15), which flags whether the AC ’97 is in the “Codec Ready”
state or not. If the “Codec Ready” bit is a 0, this indicates that
the AC ’97 is not ready for normal operation. This condition is
normal following the deassertion of power on reset, for example,
while the AC ’97’s voltage references settle. When the AC Link
“Codec Ready” indicator bit is a 1, it indicates an AC ’97
control. If the “Valid Frame” bit is a 1, this indicates that the
current audio frame contains at least one slot time of valid
data. The next 12-bit position sampled by the AC ’97
indicates which of the corresponding 12 time slots contain
valid data. In this way data streams of differing sample rates can
be transmitted across AC Link at its fixed 48 kHz SYNC rate.
Figure 8 illustrates the time-slot-based AC Link protocol.
If the AC ’97 is sampled “Codec Ready,” the next 12-bit
positions sampled by the AD1818 indicate which of the
corresponding 12 audio input slots contain valid data. In this
way data streams of differing sample rates can be transmitted
across AC Link at its fixed 48 kHz SYNC rate.
A new audio input frame begins with a low-to-high transition of
SYNC. SYNC is synchronous to the rising edge of BIT_CLK.
On the immediately following falling edge of BIT_CLK, the
AC ’97 samples the assertion of SYNC. This falling edge marks
the time when both sides of AC Link are aware of the start of a
new audio frame. On the next rising edge of BIT_CLK, the
Reserved
AC ’97 transitions SDATA_IN into the first bit position of
Slot 0 (“Codec Ready” bit). Each new bit position is presented
to AC Link on a rising edge of BIT_CLK, and subsequently
sampled by the AC ’97 controller on the following falling
edge of BIT_CLK. This sequence ensures that data transitions
and subsequent sample points for both incoming and outgoing
data streams are time aligned.
VALID
FRAME
SLOT(2)
SLOT(1)
END OF PREVIOUS
AUDIO FRAME
SYNC
BIT_CLK
SDATA_OUT
AC '97 SAMPLES SYNC ASSERTION HERE
AC '97 SAMPLES FIRST SDATA_OUT
BIT OF FRAME HERE
Figure 9. Start of an Audio Output Frame
SDATA_IN’s composite stream is MSB justified (MSB first)
with all nonvalid bit positions stuffed with 0s by the AC ’97.
SDATA_IN data is sampled on the falling edges of BIT_CLK .
Slot 1: Status Address Port
including, but not limited to, mixer settings, and power
management.
Audio input frame slot 1’s stream echoes the control register
2. (Assuming that Slots 1 and 2 had been tagged valid by the
AC ’97 during slot 0.)
Status Address Port Bit Assignments:
Reserved
(Stuffed with 0s)
for which data is being
returned)
(Stuffed with 0s)
Reserved
invalid by the AC ’97)
(Stuffed with 0s)
Bit (3:0)
Slots 3–12: Data Input Channels
Slots 3 through 12 are data input channels assigned to audio or
modem streams as defined by the Analog Codec Interface
Control/Status Register in the AD1818. Each slot is defined as
follows:
Data Input Bit Assignments:
Bit (19:4) Input Data
Reserved
(Stuffed with 0s if tagged
invalid by the AC ’97)
(Stuffed with 0s)
Bit (3:0)
Reserved
相關(guān)PDF資料 |
PDF描述 |
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| AD1819A | AC97 SoundPort Codec(AC97型聲音端口信號(hào)編解碼器) |
| AD1819BJST | AC’97 SoundPort Codec |
| AD1819 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1819B | AC’97 SoundPort Codec |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD18-182 | 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Non-Insulated; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:DISCONNECTFEMALE 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 21.08mm 5.84mm Tin |
| AD18-183 | 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Nylon; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:NON-INS FEM-187 DISC, 22-18 LEN .64 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 16.26mm 5.84mm Tin |
| AD1819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec |
| AD1819AJST | 制造商:Rochester Electronics LLC 功能描述: |
| AD1819B | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec |
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