參數(shù)資料
型號： AD1818
廠商： Analog Devices, Inc.
英文描述： PCI SoundComm DC97 Digital Controller(PCI SoundComm DC97型數(shù)字控制器)
中文描述： 的PCI SoundComm DC97數(shù)字控制器（的PCI SoundComm DC97型數(shù)字控制器）
文件頁數(shù)： 12/29頁
文件大?。?/td> 364K
代理商： AD1818
AD1818
–12–
REV. 0
7
8
9
10
11
12
13
14
15
Power-Down Interrupt. Connected to bit
in the PCI DSP Control register.
PCI Mailbox Interrupt. Writing to the
incoming mailbox register or reading from
the outgoing mailbox register via the PCI
bus can generate this interrupt.
Ring. Connected to the RING pin on the
AD1818. This is an active-HIGH interrupt.
Also connected without inversion to FLAGIN[3].
Used to connect to the RING signal from the
DAA for modem operation. If modem is not
used, can be a general purpose interrupt.
Connected to external pin. General purpose
interrupt.
48 kHz SYNC. Connects AD1818 DSP core to
the start of frame signal. Used to time data
transfers to the core for audio effects.
FIFO2 Transmit. Connected to the transmit
interrupt for the third, transmit-only FIFO.
TECHNCAL
9
10
11
12
13
14
15
16
DATA
USER0
–
PCI D1 Power-Up. Connected to the PCI
power management control. Used to bring the
DSP out of Idle while in the D1 power state.
General Purpose signals from pins.
Ring. See above. Brought to FLAGIN for ring
counting.
Phone. From DAA.
Reserved.
Analog Interface Ready. Signals that the
analog front-end is ready.
Reserved.
General Purpose Signals to output pins.
Hook. Signal to DAA to connect to phone
line. Can be used as a general purpose pin
output signal.
MICENB. Signal to enable microphone. Can be
used as a general purpose pin output signal.
PME Power-Up Request. Signal to request a
PME event on the PCI bus to wake up the
bit is set in the PCI configuration PMCSR
register and this signal is asserted.
Reserved.
FLAGIN0–1
FLAGIN3
–
–
FLAGIN2
FLAGIN4
FLAGIN5
–
–
–
FLAGIN6–7
FLAGOUT0–1 –
FLAGOUT2
–
–
FLAGOUT3
–
FLAGOUT4
–
FLAGOUT5–7 –
Table I. Interrupt Vector Table for the AD1818
Bit
0
1
2
3
4
5
Pri
1
2
3
4
5
6
7
8
Interrupt
Reset (Nonmaskable)
Power-Down (Nonmaskable)
PCI Mailbox (IRQ3)
Timer
User Interrupt 2
Ring (IRQ2)
IDMA
IRQ1
FIFO0 Receive
FIFO1 Transmit
FIFO1 Receive
48 kHz SYNC (IRQ0)
FIFO2 Transmit
PCI D1 Power-Up (User 0)
Vector Address
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
DSP to Mixer FIFOs on the AD1818
Five FIFOs provide an interface on the AD1818 between the
DSP and the mixer data bus in the AD1818 core. Two of the
FIFOs are inputs FIFOs, receiving data from the mixer data bus
into the DSP. The other three FIFOs are transmit FIFOs,
sending data from the DSP to the mixer. Each of the FIFOs are
eight words deep and 16 bits wide. Interrupts to the DSP can be
generated when some (programmable) number of words have
been received in the input FIFOs or when some (programmable)
number of words are empty in the transmit FIFOs.
The interface to the FIFOs on the DSP is simply a register
interface to the IDMD bus. Tx0, Rx0, Tx1, and Rx1 are the
primary FIFO registers in the universal register map of the DSP.
STCTL0-2, SRCTL0-1, Tx2 and ABFCTL0-2 are the FIFO
control registers and are located in the memory-mapped register
space of the DSP. The FIFOs can be used to generate interrupts to
the DSP based upon FIFO transactions or can initiate DMA
AC ’97 Interface Registers
Page
Address
10
0x7E–0x00
10
0x80
17–11
Register
Register Set
Analog Codec Interface Control/Status
Reserved
DSP Control Registers
Page
Address
18
0x00
18
0x02
18
0x06–0x04
18
0x0A–0x08
18
0x0E–0x0C
Register
DMA Transfer Count
DMA Control
Mailbox Control/Status
Incoming Mailbox
Outgoing Mailbox
Wavetable Music Synthesis
Wavetable music synthesis algorithms are run on the internal DSP.
The software wavetable engine will perform the necessary pitch
shifting and envelope generation prior to mixing the channel back
into the output streams.
System (PCI) memory is used for the storage of wavetable samples
while the wavetable engine is in use. During application initializa-
tion, the wavetable driver will load the wavetable samples into
memory for use by the AD1818. The samples need not be in
contiguous memory; instead, they will be accessed by the AD1818
via scatter-gather DMA transfers. The standard DLS download-
able sounds format is supported by the AD1818 wavetable driver.
The AD1818 wavetable driver provides all of the control required
for the chip to perform the necessary sample rate conversion,
envelope generation and effects processing. This includes MIDI
command interpretation, location of note samples in memory and
passing parameters to the AD1818 for note events.
The wavetable synthesizer has
been developed by Euphonics,
a research and development
company that specializes in
audio processing and electronic
music synthesis.
INTERRUPT STRUCTURE
Various flag input and output and interrupt pins within the
DSP core are assigned to particular functions within the
AD1818. The assignments are as follows:
PWD
–
IRQ3
–
IRQ2
–
IRQ1
–
IRQ0
–
USER1
–
EuSynth-1+
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HONICS
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