參數(shù)資料
型號(hào)： AD14060LBF-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP308
封裝： CERAMIC, QFP-308
文件頁(yè)數(shù)： 30/44頁(yè)
文件大?。?/td> 744K
代理商： AD14060LBF-4
AD14060/AD14060L
–30–
REV. A
Link Ports: 1
×
CLK Speed Operation
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Receive
Timing Requirements:
t
SLDCL
t
HLDCL
t
LCLK IW
t
LCLK RWL
t
LCLK RWH
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1
×
Operation)
LCLK Width Low
LCLK Width High
3.5
3
t
CK
6
5
3
3
t
CK
6
5
ns
ns
ns
ns
ns
Switching Characteristics:
t
DLAHC
t
DLALC
t
ENDLK
t
T DLK
LACK High Delay After CLK IN High
LACK Low Delay After LCLK High
1
LACK Enable from CLK IN
LACK Disable from CLK IN
18 + DT /2
–3
5 + DT /2
29.5 + DT /2
13.5
18 + DT /2
–3
5 + DT /2
29.5 + DT /2
13.5
ns
ns
ns
ns
21 + DT /2
21 + DT /2
T ransmit
Timing Requirements:
t
SLACH
t
HLACH
LACK Setup Before LCLK High
LACK Hold After LCLK High
18
–7
20
–7
ns
ns
Switching Characteristics:
t
DLCLK
t
DLDCH
t
HLDCH
t
LCLK T WL
t
LCLK T WH
t
DLACLK
t
ENDLK
t
T DLK
LCLK Delay After CLK IN (1
×
Operation)
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
LDAT , LCLK Enable After CLK IN
LDAT , LCLK Disable After CLK IN
16.5
3.5
17.5
3
ns
ns
ns
ns
ns
ns
ns
ns
–3
(t
CK
/2) – 2
(t
CK
/2) – 2
(t
CK
/2) + 8.5
5 + DT /2
–3
(t
CK
/2) – 1
(t
CK
/2) – 1.25
(t
CK
/2) + 8
5 + DT /2
(t
CK
/2) + 2
(t
CK
/2) + 2
(3
×
t
CK
/2) + 17.5
(t
CK
/2) + 1.25
(t
CK
/2) + 1
(3
×
t
CK
/2) + 18
21 + DT /2
21 + DT /2
Link Port Service Request Interrupts:
1
×
and 2
×
Speed Operations
Timing Requirements:
t
SLCK
LACK /LCLK Setup Before CLK IN Low
2
t
HLCK
LACK /LCLK Hold After CLK IN Low
2
10
2.5
10
2.5
ns
ns
NOT ES
1
LACK will go low with t
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2
Only required for interrupt recognition in the current cycle.
相關(guān)PDF資料
PDF描述
AD14160KB-4 Quad-SHARC DSP Multiprocessor Family
AD14160 Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 Quad-SHARC DSP Multiprocessor Family
AD14160L Quad-SHARC DSP Multiprocessor Family
AD14160LBB-4 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD14160 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160KB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160LBB-4 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
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