參數(shù)資料
型號： AD14060LBF-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP308
封裝： CERAMIC, QFP-308
文件頁數(shù)： 22/44頁
文件大?。?/td> 744K
代理商： AD14060LBF-4
AD14060/AD14060L
–22–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
SADRI
t
HADRI
t
SRWLI
t
HRWLI
t
RWHPI
t
SDAT WH
t
HDAT WH
Address,
SW
Setup Before CLK IN
Address,
SW
Hold Before CLK IN
RD
/
WR
Low Setup Before CLK IN
1
RD
/
WR
Low Hold After CLK IN
RD
/
WR
Pulse High
Data Setup Before
WR
High
Data Hold After
WR
High
15.5 + DT /2
15.5 + DT /2
ns
ns
ns
ns
ns
ns
ns
4.5 + DT /2
4.5 + DT /2
9.5 + 5DT /16
–3.5 – 5DT /16
3
5.5
1.5
9.5 + 5DT /16
–3.5 – 5DT /16
3
5.5
1.5
8 + 7DT /16
8 + 7DT /16
Switching Characteristics:
t
SDDAT O
t
DAT T R
t
DACK AD
t
ACK T R
Data Delay After CLK IN
Data Disable After CLK IN
2
ACK Delay After Address,
SW
3
ACK Disable After CLK IN
3
20 + 5DT /16
8 – DT /8
10
7 – DT /8
20 + 5DT /16
8 – DT /8
10
7 – DT /8
ns
ns
ns
ns
0 – DT /8
0 – DT /8
–1 – DT /8
–1 – DT /8
NOT ES
1
t
SRWLI
(min) = 9.5 + 5DT /16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled,
t
SRWLI
(min) = 4 + DT /8.
2
See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.
3
t
DACK AD
is true only if the address and
SW
inputs have setup times (before CLK IN) greater than 10.5 + DT /8 and less than 18.5 + 3DT /4. If the address and
SW
inputs have
setup times greater than 19 + 3DT /4, then ACK is valid 15 + DT /4 (max) after CLK IN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
ACK T R
.
Synchronous Read/Write—Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
T he bus master must meet these (bus slave) timing requirements.
CLKIN
ADDRESS
SW
ACK
RD
DATA
(OUT)
WR
WRITE ACCESS
t
SADRI
t
HADRI
t
DACKAD
t
ACKTR
t
RWHPI
t
HRWLI
t
SRWLI
t
SDDATO
t
DATTR
t
SRWLI
t
HRWLI
t
RWHPI
t
HDATWH
t
SDATWH
DATA
(IN)
READ ACCESS
Figure 17. Synchronous Read/Write—Bus Slave
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