參數(shù)資料
型號(hào)： AD14060LBF-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP308
封裝： CERAMIC, QFP-308
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 744K
代理商： AD14060LBF-4
AD14060/AD14060L
–20–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
SSDAT I
t
HSDAT I
t
DAAK
t
SACK C
t
HACK C
Data Setup Before CLK IN
Data Hold After CLK IN
ACK Delay After Address,
MS
x,
SW
,
BMS
1, 2
ACK Setup Before CLK IN
2
ACK Hold After CLK IN
3 + DT /8
4 – DT /8
3 + DT /8
4 – DT /8
ns
ns
ns
ns
ns
13.5 + 7 DT /8 + W
13.5 + 7 DT /8 + W
6.5 + DT /4
–0.5 – DT /4
6.5 + DT /4
–0.5 – DT /4
Switching Characteristics:
t
DADRO
Address,
MS
x,
BMS
,
SW
Delay After CLK IN
1
t
HADRO
Address,
MS
x,
BMS
,
SW
Hold After CLK IN
t
DPGC
PAGE Delay After CLK IN
t
DRDO
RD
High Delay After CLK IN
t
DWRO
WR
High Delay After CLK IN
t
DRWL
RD
/
WR
Low Delay After CLK IN
t
SDDAT O
Data Delay After CLK IN
t
DAT T R
Data Disable After CLK IN
3
t
DADCCK
ADRCLK Delay After CLK IN
t
ADRCK
ADRCLK Period
t
ADRCK H
ADRCLK Width High
t
ADRCK L
ADRCLK Width Low
8 – DT /8
8 – DT /8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–1 – DT /8
9 + DT /8
–2 – DT /8
–3 – 3DT /16 5 – 3DT /16
8 + DT /4
–1 – DT /8
9 + DT /8
–2 – DT /8
–3 – 3DT /16 5 – 3DT /16
8 + DT /4
17 + DT /8
5 – DT /8
17 + DT /8
5 – DT /8
13.5 + DT /4
20 + 5DT /16
8 – DT /8
11 + DT /8
13.5 + DT /4
20 + 5DT /16
8 – DT /8
11 + DT /8
0 – DT /8
4 + DT /8
t
CK
(t
CK
/2 – 2)
(t
CK
/2 – 2)
0 – DT /8
4 + DT /8
t
CK
(t
CK
/2 – 2)
(t
CK
/2 – 2)
W = (number of Wait states specified in WAIT register)
×
t
CK
.
NOT ES
1
For
MS
x,
SW
,
BMS
, the falling edge is referenced.
2
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACK C
.
3
See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLK IN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). T hese
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). T he
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
相關(guān)PDF資料
PDF描述
AD14160KB-4 Quad-SHARC DSP Multiprocessor Family
AD14160 Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 Quad-SHARC DSP Multiprocessor Family
AD14160L Quad-SHARC DSP Multiprocessor Family
AD14160LBB-4 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD14160 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160KB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160LBB-4 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
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