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參數(shù)資料
| 型號： | AD14060LBF-4 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, CQFP308 |
| 封裝： | CERAMIC, QFP-308 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 744K |
| 代理商： | AD14060LBF-4 |
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AD14060/AD14060L
–12–
REV. A
T ARGE T BOARD CONNE CT OR FOR E Z-ICE PROBE
T he ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JT AG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. T he EZ-ICE probe
requires that the AD14060/AD14060L’s CLK IN (optional),
T MS, T CK ,
TRST
, T DI, T DO,
EMU
and GND signals be
made accessible on the target system via a 14-pin connector (a
pin strip header) such as that shown in Figure 6. T he EZ-ICE
probe plugs directly onto this connector for chip-on-board emu-
lation. You must add this connector to your target board design
if you intend to use the ADSP-2106x EZ-ICE. T he length of
the traces between the connector and the AD14060/
AD14060L’s JT AG pins should be as short as possible.
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
CLKIN (OPTIONAL)
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
Emulator (J umpers in Place)
T he 14-pin, 2-row pin strip header is keyed at the Pin 3 location;
Pin 3 must be removed from the header. T he pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1
×
0.1 inches. Pin strip headers are available from
vendors such as 3M, McK enzie and Samtec.
T he BT MS, BT CK ,
BTRST
and BT DI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 6. If you are not going to use the test access port for
board testing, tie
BTRST
to GND and tie or pull up BT CK to
V
DD
. T he
TRST
pin must be asserted after power-up (through
BTRST
on the connector) or held low for proper operation of
the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the EZ-ICE probe.
T he JT AG signals are terminated on the EZ-ICE probe as follows:
Signal
T ermination
Driven through 22
Resistor (16
μ
A–3.2
μ
A Driver)
Driven at 10 MHz through 22
Resistor (16
μ
A–
3.2
μ
A Driver)
Driven by Open-Drain Driver* (Pulled Up by On-Chip
20 k
resistor)
Driven by 16
μ
A–3.2
μ
A Driver
One T T L Load, No T ermination
One T T L Load, No T ermination (Optional Signal)
4.7 k
Pull-Up Resistor, One T T L Load (Open-Drain
Output from ADSP-2106x)
T MS
T CK
TRST
T DI
T DO
CLK IN
EMU
*
TRST
is driven low until the EZ-ICE probe is turned on by the EZ-ICE
software (after the invocation command).
Figure 7 shows JT AG scan path connections for the multi-
processor system.
Connecting CLK IN to Pin 4 of the EZ-ICE header is optional.
T he emulator only uses CL K IN when directed to perform
SHARC_A
TDI
TDO
T
T
E
T
EZ-ICE
JTAG
CONNECTOR
TDI
TCK
TMS
EMU
TRST
TDO
CLKIN
OTHER
JTAG
CONTROLLER
SHARC_B
TDI
TDO
T
T
E
T
SHARC_C
TDI
TDO
T
T
E
T
SHARC_D
TDI
TDO
T
T
E
T
JTAG DEVICE
(OPTIONAL)
TDI
TDO
T
T
T
TDI
TDO
T
T
E
T
ADSP-2106x
#n
OPTIONAL
Figure 7. J TAG Scan Path Connections for the AD14060/AD14060L
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相關(guān)代理商/技術(shù)參數(shù) |
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