- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373857 > AD14060L (Analog Devices, Inc.) ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% PDF資料下載
參數(shù)資料
| 型號： | AD14060L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | 四SHARC處理器DSP的多處理器家族 |
| 文件頁數(shù)： | 38/44頁 |
| 文件大?。?/td> | 744K |
| 代理商： | AD14060L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD14060/AD14060L
–38–
REV. A
(per data line). T he hold time will be t
DECAY
plus the minimum
disable time (i.e., t
HDWD
for the write cycle).
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
–
V
V
OL (MEASURED)
+
V
t
DECAY
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
ENA
Figure 27. Output Enable/Disable
+1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 28. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
INPUT OR
OUTPUT
1.5V
1.5V
Figure 29. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). T he delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 30 and 31
show how output rise time varies with capacitance. Figure 32
graphically shows how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see the previous section Output Disable
T ime under T est Conditions.) T he graphs of Figures 30, 31 and
32 may not be linear outside the ranges shown.
LOAD CAPACITANCE – pF
16.0
8.0
00
200
20
40
60
80
100
120
140
160
180
14.0
12.0
4.0
3.7
2.0
1.1
10.0
6.0
14.7
7.4
FALL TIME
RISE TIME
R
(
Figure 30. Typical Output Rise Time (10%–90% V
DD
)
vs. Load Capacitance (V
DD
= 5 V)
LOAD CAPACITANCE – pF
0
0
20
40
60
80
100
120
RISE TIME
FALL TIME
140
160
180
200
0.5
0.6
1.0
1.5
2.0
2.5
3.0
3.5
R
1.6
2.9
Figure 31. Typical Output Rise Time (0.8 V –2.0 V)
vs. Load Capacitance (V
DD
= 5 V)
LOAD CAPACITANCE – pF
O
5
–1
25
200
50
75
100
125
150
175
4
3
2
1
NOMINAL
–0.7
4.5
Figure 32. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature) (V
DD
= 5 V)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD14060LBF-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160KB-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160 | Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160L | Quad-SHARC DSP Multiprocessor Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD14060LBF-4 | 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| AD14160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。