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參數(shù)資料
| 型號(hào)： | AD14060L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | 四SHARC處理器DSP的多處理器家族 |
| 文件頁(yè)數(shù)： | 33/44頁(yè) |
| 文件大?。?/td> | 744K |
| 代理商： | AD14060L |
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AD14060/AD14060L
–33–
REV. A
Serial Ports
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
E xternal Clock
Timing Requirements:
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLK W
t
SCLK
T FS/RFS Setup Before T CLK /RCLK
1
T FS/RFS Hold After T CLK /RCLK
1, 2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
T CLK /RCLK Width
T CLK /RCLK Period
4
4.5
2
4.5
9.5
t
CK
4
4.5
2
4.5
9
t
CK
ns
ns
ns
ns
ns
ns
Internal Clock
Timing Requirements:
t
SFSI
t
HFSI
t
SDRI
t
HDRI
T FS Setup Before T CLK
1
; RFS Setup Before RCLK
1
T FS/RFS Hold After T CLK /RCLK
1, 2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
9
1
4
3
9
1
4
3
ns
ns
ns
ns
E xternal or Internal Clock
Switching Characteristics:
t
DFSE
RFS Delay After RCLK (Internally Generated RFS)
3
t
HFSE
RFS Hold After RCLK (Internally Generated RFS)
3
14
14
ns
ns
3
3
E xternal Clock
Switching Characteristics:
t
DFSE
T FS Delay After T CLK (Internally Generated T FS)
3
t
HFSE
T FS Hold After T CLK (Internally Generated T FS)
3
t
DDT E
T ransmit Data Delay After T CLK
3
t
HDT E
T ransmit Data Hold After T CLK
3
14
14
ns
ns
ns
ns
3
3
17
17
5
5
Internal Clock
Switching Characteristics:
t
DFSI
T FS Delay After T CLK (Internally Generated T FS)
3
t
HFSI
T FS Hold After T CLK (Internally Generated T FS)
3
t
DDT I
T ransmit Data Delay After T CLK
3
t
HDT I
T ransmit Data Hold After T CLK
3
t
SCLK IW
T CLK /RCLK Width
5
5
ns
ns
ns
ns
–1.5
–1.5
8
8
0
(SCLK /2) – 2
0
(SCLK /2) – 2.5 (SCLK /2) + 2.5 ns
(SCLK /2) + 2
E nable and T hree-State
Switching Characteristics:
t
DDT EN
Data Enable from External T CLK
3
t
DDT T E
Data Disable from External T CLK
3
t
DDT IN
Data Enable from Internal T CLK
3
t
DDT T I
Data Disable from Internal T CLK
3
t
DCLK
T CLK /RCLK Delay from CLK IN
t
DPT R
SPORT Disable After CLK IN
3.5
4
ns
ns
ns
ns
ns
ns
11.5
11.5
0
0
3
23 + 3DT /8
18
3
23 + 3DT /8
18
E xternal Late Frame Sync
Switching Characteristics:
t
DDT LFSE
Data Delay from Late External T FS or
External RFS with MCE = 1, MFD = 0
4
t
DDT ENFS
Data Enable from late FS or MCE = 1, MFD = 0
4
13
13.8
ns
3.0
3.5
ns
T o determine whether communication is possible between two devices at clock speed
n,
the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOT ES
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. T FS hold after T CK for late external T FS is 0.5 ns minimum from drive edge.
3
Referenced to drive edge.
4
MCE = 1, T FS enable and T FS valid follow t
DDT LFSE
and t
DDT ENFS
.
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