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參數(shù)資料
| 型號： | AD14060L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | 四SHARC處理器DSP的多處理器家族 |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 744K |
| 代理商： | AD14060L |
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AD14060/AD14060L
–28–
REV. A
transfer is controlled by ADDR
31-0
,
RD
,
WR
,
MS
3-0
, and ACK
(not
DMAG
). For Paced Master mode, the “Memory Read–Bus
Master”, “Memory Write–Bus Master”, and “Synchronous
Read/Write–Bus Master” timing specifications for ADDR
31-0
,
RD
,
WR
,
MS
3-0
,
SW
, PAGE, DAT A
47-0
, and ACK also apply.
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
SDRLC
t
SDRHC
t
WDR
t
SDAT DGL
t
HDAT IDG
t
DAT DRH
t
DMARLL
t
DMARH
DMAR
x Low Setup Before CLK IN
1
DMAR
x High Setup Before CLK IN
1
DMAR
x Width Low (Nonsynchronous)
Data Setup After
DMAG
x Low
2
Data Hold After
DMAG
x High
Data Valid After
DMAG
x High
2
DMAG
x Low Edge to Low Edge
DMAG
x Width High
5
5
6
5
5
6
ns
ns
ns
ns
ns
ns
ns
ns
9.5 + 5DT /8
9.5 + 5DT /8
2.5
2.5
15.5 + 7DT /8
15.5 + 7DT /8
23 + 7DT /8
6
23 + 7DT /8
6
Switching Characteristics:
t
DDGL
t
WDGH
t
WDGL
t
HDGC
t
VDAT DGH
t
DAT RDGH
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
DGWR
t
DADGH
t
DDGHA
DMAG
x Low Delay After CLK IN
DMAG
x High Width
DMAG
x Low Width
DMAG
x High Delay After CLK IN
Data Valid Before
DMAG
x High
3
Data Disable After
DMAG
x High
4
WR
Low Before
DMAG
x Low
DMAG
x Low Before
WR
High
WR
High Before
DMAG
x High
RD
Low Before
DMAG
x Low
RD
Low Before
DMAG
x High
RD
High Before
DMAG
x High
DMAG
x High to
WR
,
RD
,
DMAG
x Low
Address/Select Valid to
DMAG
x High
Address/Select Hold after
DMAG
x High
9 + DT /4
6 + 3DT /8
12 + 5DT /8
–2 – DT /8
7.5 + 9DT /16
–0.5
–0.5
9.5 + 5DT /8 + W
0.5 + DT /16
–0.5
10.5 + 9DT /16 + W
–0.5
4.5 + 3DT /8 + HI
16 + DT
–1
16 + DT /4
9 + DT /4
6 + 3DT /8
12 + 5DT /8
–2 – DT /8
7.5 + 9DT /16
–0.5
–0.5
9.5 + 5DT /8 + W
0.5 + DT /16
–0.5
10.5 + 9DT /16 + W
–0.5
4.5 + 3DT /8 + HI
16 + DT
–1
16 + DT /4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7 – DT /8
7 – DT /8
8
2.5
8
2.5
3.5 + DT /16
2
3.5 + DT /16
2
3.5
3.5
W = (number of wait states specified in WAIT register)
×
t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOT ES
1
Only required for recognition in the current cycle.
2
t
is the data setup requirement if
DMAR
x is not being used to hold off completion of a write. Otherwise, if
DMAR
x low holds off completion of the write, the
data can be driven t
DAT DRH
after
DMAR
x is brought high.
3
t
is valid if
DMAR
x is not being used to hold off completion of a read. If
DMAR
x is used to prolong the read, then t
VDAT DGH
= 7.5 + 9DT /16 + (n
×
t
CK
)
where
n
equals the number of extra cycles that the access is prolonged.
4
See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.
DMA Handshake
T hese specifications describe the three DMA handshake modes.
In all three modes
DMAR
is used to initiate transfers. For hand-
shake mode,
DMAG
controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR
31-0
,
RD
,
WR
,
SW
, PAGE,
MS
3-0
,
ACK , and
DMAG
signals. For Paced Master mode, the data
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