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參數(shù)資料
| 型號： | AD14060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | 四SHARC處理器DSP的多處理器家族 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大小： | 744K |
| 代理商： | AD14060 |
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AD14060/AD14060L
–22–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
SADRI
t
HADRI
t
SRWLI
t
HRWLI
t
RWHPI
t
SDAT WH
t
HDAT WH
Address,
SW
Setup Before CLK IN
Address,
SW
Hold Before CLK IN
RD
/
WR
Low Setup Before CLK IN
1
RD
/
WR
Low Hold After CLK IN
RD
/
WR
Pulse High
Data Setup Before
WR
High
Data Hold After
WR
High
15.5 + DT /2
15.5 + DT /2
ns
ns
ns
ns
ns
ns
ns
4.5 + DT /2
4.5 + DT /2
9.5 + 5DT /16
–3.5 – 5DT /16
3
5.5
1.5
9.5 + 5DT /16
–3.5 – 5DT /16
3
5.5
1.5
8 + 7DT /16
8 + 7DT /16
Switching Characteristics:
t
SDDAT O
t
DAT T R
t
DACK AD
t
ACK T R
Data Delay After CLK IN
Data Disable After CLK IN
2
ACK Delay After Address,
SW
3
ACK Disable After CLK IN
3
20 + 5DT /16
8 – DT /8
10
7 – DT /8
20 + 5DT /16
8 – DT /8
10
7 – DT /8
ns
ns
ns
ns
0 – DT /8
0 – DT /8
–1 – DT /8
–1 – DT /8
NOT ES
1
t
SRWLI
(min) = 9.5 + 5DT /16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled,
t
SRWLI
(min) = 4 + DT /8.
2
See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.
3
t
DACK AD
is true only if the address and
SW
inputs have setup times (before CLK IN) greater than 10.5 + DT /8 and less than 18.5 + 3DT /4. If the address and
SW
inputs have
setup times greater than 19 + 3DT /4, then ACK is valid 15 + DT /4 (max) after CLK IN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
ACK T R
.
Synchronous Read/Write—Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
T he bus master must meet these (bus slave) timing requirements.
CLKIN
ADDRESS
SW
ACK
RD
DATA
(OUT)
WR
WRITE ACCESS
t
SADRI
t
HADRI
t
DACKAD
t
ACKTR
t
RWHPI
t
HRWLI
t
SRWLI
t
SDDATO
t
DATTR
t
SRWLI
t
HRWLI
t
RWHPI
t
HDATWH
t
SDATWH
DATA
(IN)
READ ACCESS
Figure 17. Synchronous Read/Write—Bus Slave
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD14060L | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD14060LBF-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160KB-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160 | Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | Quad-SHARC DSP Multiprocessor Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD14060BF-4 | 制造商:Analog Devices 功能描述:DSP Fixed-Point/Floating-Point 32-Bit 40MHz 40MIPS 308-Pin CQFP 制造商:Rochester Electronics LLC 功能描述:QUAD 21060 INDUSTRIAL TEMP, 40 MHZ, 5 V - Bulk |
| AD14060L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14060LBF-4 | 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| AD14160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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