參數(shù)資料
型號: AD14060
廠商: Analog Devices, Inc.
英文描述: ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
中文描述: 四SHARC處理器DSP的多處理器家族
文件頁數(shù): 15/44頁
文件大小: 744K
代理商: AD14060
AD14060/AD14060L
–15–
REV. A
E SD SE NSIT IVIT Y
T he AD14060/AD14060L modules are ESD (electrostatic discharge) sensitive devices. Electro-
static charges readily accumulate on the human body and equipment and can discharge without
detection. Permanent damage may occur to devices subjected to high energy electrostatic
discharges.
T he ADSP-21060 processors include proprietary ESD protection circuitry to dissipate high
energy discharges. Per method 3015 of MIL -ST D-883, the ADSP-21060 processors have been
classified as a Class 2 device.
Proper ESD precautions are recommended to avoid performance degradation or loss of function-
ality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination socket before devices are removed.
ABSOLUT E MAX IMUM RAT INGS*
Supply Voltage (5 V) . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Supply Voltage (3.3 V) . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction T emperature Under Bias . . . . . . . . . . . . . . . . 130
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead T emperature (5 seconds) . . . . . . . . . . . . . . . . . +280
°
C
*Stresses greater than those listed above may cause permanent damage to the
device. T hese are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
TIMNGSPECIFICATIONS
GE NE RAL NOT E S
T his data sheet represents production released specifications for
the AD14060 (5 V), and for the AD14060L (3.3 V). T he
ADSP-21060 die components are 100% tested, and the assembled
AD14060/AD14060L units are again extensively tested at-
speed, and across-temperature. Parametric limits were estab-
lished from the ADSP-21060 characterization followed by
further design/analysis of the AD14060/AD14060L package
characteristics. T he specifications shown are based on a CLK IN
frequency of 40 MHz (t
CK
= 25 ns). T he DT derating allows
specifications at other CLK IN frequencies (within the min-max
range of the t
CK
specification; see “Clock Input” below). DT is the
difference between the actual CLK IN period and a CLK IN period
of 25 ns:
DT
=
t
CK
– 25
ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
Switching Characteristics
specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. Y ou can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing Requirements
apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. T iming requirements guarantee that the processor
operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drain
WARNNG
ESD SENSITIVE DEVICE
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