參數(shù)資料
型號： AD14060
廠商： Analog Devices, Inc.
英文描述： ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
中文描述： 四SHARC處理器DSP的多處理器家族
文件頁數(shù)： 10/44頁
文件大?。?/td> 744K
代理商： AD14060
AD14060/AD14060L
–10–
REV. A
Pin
T ype
Function
T CLK y1
I/O
Transmit Clock
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) T CLK
pin has a 50 k
internal pull-up resistor.
Receive Clock
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK
pin has a 50 k
internal pull-up resistor.
Transmit Frame Sync
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
Receive Frame Sync
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
Flag Pins.
(FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
Flag Pins.
(FLAG1 common to all SHARCs) Configured via control bits internal to individual ADSP-
21060s as either an input or output. As an input, it can be tested as a condition. As an output, it can be
used to signal external peripherals.
Flag Pins.
(FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
Interrupt Request Lines.
(Individual
IRQ
2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)
May be either edge-triggered or level-sensitive.
DMA Request 1
(DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Request 2
(DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 1
(DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 2
(DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
Link Port Clock
(y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
1
. Each LyxCLK pin has a 50 k
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160.
L ink Port D ata
(y = SHARC_A, B, C, D; x = L ink Ports 1, 3, 4)
1
. Each L yxDAT pin has a
50 k
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
Link Port Acknowledge
(y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
1
. Each LyxACK pin has a
50 k
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
E PROM Boot Select.
(SHARC_A) When EBOOT A is high, SHARC_A is configured for booting from
an 8-bit EPROM. When EBOOT A is low, the L BOOT A and
BMSA
inputs determine booting mode
for SHARC_A. See the following table. T his signal is a system configuration selection which should
be hardwired.
Link Boot.
When LBOOT A is high, SHARC_A is configured for link port booting. When LBOOT A is
low, SHARC_A is configured for host processor booting or no booting. See the following table. T his
signal is a system configuration selection which should be hardwired.
Boot Memory Select.
Output:
Used as chip select for boot EPROM devices (when EBOOT A = 1,
LBOOT A = 0). In a multiprocessor system,
BMS
is output by the bus master.
Input:
When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. T his input is a system configuration selection which should be hardwired.
E PROM Boot Select.
(Common to SHARC_B, SHARC_C, SHARC_D) When EBOOT BCD is high,
SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOT BCD is low, the
LBOOT BCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. T his signal is a system configuration selection which should be hardwired.
LINK Boot.
(Common to SHARC_B, SHARC_C, SHARC_D) When LBOOT BCD is high, SHARC_B, C,
D are configured for link port booting. When LBOOT BCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. T his signal is a system configuration selec-
tion which should be hardwired.
RCLK y1
I/O
T FSy1
RFSy1
FLAGy0
I/O
I/O
I/O/A
FLAG1
I/O/A
FLAGy2
I/O/A
IRQ
y2-0
I/A
DMAR1
DMAR2
DMAG1
DMAG2
LyxCLK
I/A
I/A
O/T
O/T
I/O
LyxDAT 3-0
I/O
LyxACK
I/O
EBOOT A
I
LBOOT A
I
BMSA
I/O/T
2
EBOOT BCD
I
LBOOT BCD
I
相關(guān)PDF資料
PDF描述
AD14060L ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14060LBF-4 Quad-SHARC DSP Multiprocessor Family
AD14160KB-4 Quad-SHARC DSP Multiprocessor Family
AD14160 Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 Quad-SHARC DSP Multiprocessor Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD14060BF-4 制造商:Analog Devices 功能描述:DSP Fixed-Point/Floating-Point 32-Bit 40MHz 40MIPS 308-Pin CQFP 制造商:Rochester Electronics LLC 功能描述:QUAD 21060 INDUSTRIAL TEMP, 40 MHZ, 5 V - Bulk
AD14060L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14060LBF-4 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
AD14160 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
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