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參數(shù)資料
| 型號： | A42MX16-2CQ100B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 45/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2CQ100B |
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30
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 4 - CCS: Core Clock Select Bit
This bit selects between FRC-oscillator clock and all other clock sources. The CCS bit must be
written to logic one to enable the mode selected with the CMM[1..0] bits. If the CCS bit is written
to logic zero, the FRC-oscillator clock is enabled. When the CCS bit is logic one, the CMM[1..0]
bits in CMCR must not be changed. After external clock fail detection the CCS bit is written to
zero.
Bit 3 - CMONEN: Clock MONitoring ENable
This bit controls the clock monitoring. The CMONEN bit must be written to logic one to enable
the clock monitoring, if the CMONEN bit is written to logic zero, clock monitoring is always
disabled.
Bit 2 - SRCD: Slow RC oscillator (SRC) Disable Bit
This bit controls the SRC oscillator used as clock source for the WatchDog (also called as
WDRC). The SRCD bit must be written to logic one to disable (stop) the SRC, and if the SRCD
bit is written to logic zero, the SRC is always enabled (running). The SRC-oscillator cannot be
disabled if the fuse bit WDRCON is programmed.
Bits 1..0 - CMM1..0: Clock Management Mode Bits 1 - 0
These bits select the input clock source (CL) of the System Clock Prescaler. Bits CMM1 and
CMM0 are not affected by an external clock fail. Before changing the CMM1..0 bits, CCS must
first be cleared. After the CMM1..0 bits have been changed, CCS can be set to logic one.
Table 3-3.
External Clock Input Select Bit Description
ECINS
Description
0PC0
→External Input clock 0 (ECIN0)
1PD4
→External Input clock 1 (ECIN1)
Table 3-4.
Core Clock Select Bit Description
CCS
Description
0
The FRC-oscillator generates CL
1
The SRC-oscillator or an external clock source (ECL) generates dependent on the
setting of CMM[1..0] bits.
Table 3-5.
Clock Source of the System Clock Prescaler Select Bit Description
Mode
Clock Source for System Clock Prescaler (CL)
CMM1
CMM0
CCS = 0
CCS = 1
0
FRC
Reserved
1
0
1
FRC
Reserved
21
0
FRC
SRC
31
1
FRC
ECL
相關PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2CQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2CQ100B | 40MX and 42MX FPGA Families |
| A42MX02-2CQ100ES | 40MX and 42MX FPGA Families |
| A42MX04-2CQ100ES | Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:Stripped End Leads; Cable Length:2m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes |
| A42MX09-2CQ100ES | Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:2m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2CQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2PL100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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