參數(shù)資料
型號: A42MX16-2CQ100B
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 114/120頁
文件大?。?/td> 854K
代理商: A42MX16-2CQ100B
93
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bits 2 to 0 – T2CS2..0: Timer2 Clock Select Bits 2 to 0
The T2CS2, T2CS1, and T2CS0 bits select the input clock (CL2) of theTimer2, shown in Table
3.13.5.15
Timer2 Mode Register B – T2MRB
Bit 7 - T2SSIE: Timer2 SSI Enable Bit
This bit must be set to enable any SSI operation. When this bit is written to low, the SSI is
disabled.
Bit 6 - T2CPOL: Timer2 Clock POLarity for SSI Shift Clock
When this bit is written to one, SCLK is high when idle. When T2CPOL is written to zero, SCLK
is low when idle. Refer to Figure 3-36 for an example. The T2CPOL functionality is summarized
below:
Figure 3-36. SSI Data Transfer Format
Table 3-40.
Timer2 Input Clock Select Bit Description
T2CS2
T2CS1
T2CS0
Input Clock (CL2) of TCNT2
00
0
CLT
00
1
CLKI/O
01
0
CLKT0
01
1
CLKT1
10
0
CLKT3
10
1
T2I
11
0
T3I
1
SENO
Bit
7
654
3210
T2SSIE T2CPOL
-
T2TOP
T2M3
T2M2
T2M1
T2M0
T2MRB
Read/Write
R/WR/W
R
R/W
R/WR/W
Initial Value
0
000
0000
SCLK
(T2CPOL = 1)
SO-PIN
SI-PIN
SAMPLE
SO/SI
SCLK
(T2CPOL = 0)
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