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參數(shù)資料
| 型號(hào)： | A42MX16-2BG100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 15/120頁 |
| 文件大小： | 854K |
| 代理商： | A42MX16-2BG100I |
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111
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.7.12
Timer3 Modes
Mode 1: Timer/Counter Mode
In Timer/Counter mode Timer3/Counter3 can be supplied with internal/external clocks. The port
pin PB1 can be used as general digital I/O. An example of this mode is shown in Figure 3-50.
Figure 3-50. Timer/Counter Mode, Timing Diagram
Mode 2: Toggle Mode
The modulator consists of a toggle flip-flop (T3), a control logic with the Timer3 Mode Register B
(T3MRB) and an interface to the output pin (T3O). The modulator have different modes, which
can be selected with the T3M[2..0] bits in the T3MRB register.
Figure 3-51. Timer3 Modulator Stage
In Toggle Mode the Timer3/Counter3 can be supplied with internal/external clocks. With every
clock CLK
T3 the output of the flip-flop T3 (M30) toggles. The signal M30 will be directed to the
output T3O.
Mode 3: Burst modulation Mode with Timer2 (M2)
In Burst modulation mode Timer3/Counter3 can be supplied with internal/external clocks. In this
mode you can burst (gate) the toggled clock of CLK
T3 (M30) with the modulator output of Timer2
(M2), see Figure 3-51 (M31 = M30 and M2). The signal M31 will be directed to the output T3O.
Mode 4/5: Capture Mode
The Timer3/Counter3 can be supplied with internal/external clocks. The trigger source for the
input capture signal can be selected by the T3ICS[1..0] bits in theT3MRA register and addition-
ally the active edge for this input signal can be selected with the T3CE[1..0] in the T3MRA
register. In Mode 4 the port pin PB1 can be used as general digital I/O. In Mode 5 the output sig-
nal of toggle flip-flop (M30) will be directed to T3O.
Mode 6: Sensor Measurement Mode together with Timer2
See Figure 3-46 on page 100 (Mode 13 description of Timer2).
In Sensor measurement mode it is recommended to enable Capture Noise Canceler of Timer3
to get correct measure results.
T3E
T3CNT
CLK
T3
T3COMA/B
T3CORA/B
CL3
2
12
01
2
0
12
0
10
0
12
0
CLKT3
T3O
Co
n
tr
o
l/Interf
a
ce
T3TOP
M30
M2
M31
T3
T3MRB
T3M[2..0]
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| A42MX24-2BG100I | 40MX and 42MX FPGA Families |
| A42MX36-2BG100I | 40MX and 42MX FPGA Families |
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| A42MX16-2PQ100 | 40MX and 42MX FPGA Families |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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