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參數(shù)資料
| 型號： | A42MX16-2BG100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 108/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2BG100I |
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88
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.5.6
Timer2 Registers
Timer2 has five control/mode registers, an interrupt flag register, a modulator receive and trans-
mit buffer register, a 16-bit compare register, and a 16-bit capture register.
3.13.5.7
Timer2 Control Register A – T2CRA
Bit 7 - T2E: Timer2 Enable Bit
This bit controls the Timer2 block. The T2E bit must be written to logic one to enable Timer2,
and if the T2E bit is written to logic zero, the Timer2 is disabled.
Bit 6 - T2TS: Timer2 Toggle with Start Bit
The T2TS bit must be written to logic one if the modulator output of Timer2 is toggled when the
timer is enabled with T2E. If the T2TS bit is written to logic zero, the modulator output of Timer2
is not toggled with the timer enabled.
Bit 5 - T2ICS: Timer Input Capture Select Bit
The T2ICS bit selects the input capture signal of the Timer2, shown in Table 3-37.
Bit4 - Res: Reserved Bit
This bit is reserved bit at the ATA6289 and will always read as zero.
Bit 3 - T2CRM: Timer2 Compare Reset Mask Bit
The T2CRM bit must be written to logic one to enable the counter reset if a match of the counter
with the compare register occurs, and if the T2CRM bit is written to logic zero, the counter reset
is disabled.
Bit 2 - T2CR: Timer2 Counter Reset
The T2CR Bit resets the Counter2 asynchronously if this bit is set to logic 1.
Bit 1 - T2CTM: Timer2 Compare Toggle Mask Bit
The T2CTM bit must be written to logic one to enable the compare toggle, and if the T2CTM bit
is written to logic zero, the compare toggle is disabled. A match of the counter with the compare
register toggles the output flip-flop in the modulator of the Timer2.
Bit 0 - T2OTM: Timer2 Overflow Toggle Mask Bit
The T2OTM bit must be written to logic one to enable the overflow toggle, and if the T2OTM bit
is written to logic zero, the overflow toggle is disabled. A counter overflow toggles the output
flip-flop in the modulator of the Timer2.
Bit
7
6
543
2
1
0
T2E
T2TS
T2ICS
T2CRM
T2CR
T2CTM
T2OTM
T2CRA
Read/Write
R/WR/W
R/W
R
R/WR/W
Initial Value
0
000
0
Table 3-37.
Input Capture Signal Select Bit Description
T2ICS
Description
0CLKT1
1T2ICP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2BG100I | 40MX and 42MX FPGA Families |
| A42MX36-2BG100I | 40MX and 42MX FPGA Families |
| A42MX09-2PQ100 | 40MX and 42MX FPGA Families |
| A42MX16-2PQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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