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參數(shù)資料
| 型號： | A42MX16-2BG100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 106/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2BG100I |
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86
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.5.5
Modulator Synchronous Serial Interface (SSI)
The Synchronous Serial Interface (SSI) allows synchronous data transfer between the ATA6289
and the peripheral devices and also the generation of Biphase code, Manchester code or PWM
code together with the serial data output into a continuous serial stream of data. The SSI consist
a 8-bit shift register (SR), a SSI I/O data register (T2MDR), a mode register (T2MRB), a status
register (T2IFR), an interrupt mask register (T2IMR), an input clock (CLK
T2), two serial data I/O
lines (SI and SO), a shift clock I/O line (SCLK) and three different interrupt request signals
(T2RXB, T2TXB, T2TXC). The Figure 3-34 shows the Synchronous Serial Interface (SSI).
The SSI includes following features:
Full-duplex, Three-wire Synchronous Data Transfer
Only Master Operation
MSB First Data Transfer
Generation of a Continuous Serial Stream of Data
End of Transmission Interrupt Flag
Figure 3-34. Synchronous Serial Interface (SSI)
The SSI contains a 8-bit shift register with two associated 8-bit buffers - the receive buffer
T2MDR (RXD) to capture incoming serial data and a transmit buffer T2MDR (TXD) to store the
data for the serial data output. Both buffers share the same I/O addresses labeled as Timer2
Modulator Data Register or T2MDR and can be directly accessed by software. The SSI automat-
ically controls the data transfer between transmit and receive buffer and the 8-Bit shift register.
In that way either single byte transfers or continuous bit streams can be supported.
The SSI is always master. The required clock for the data interchange is accessible on the
SCLK line from the Timer2/counter2 stage output clock (CLK
T2). SCLK is half the clock of CLKT2.
With this additional division by 2 we ensure a duty cycle of 50% for SCLK which is important for
the SSI data transfer (see Figure 3-36 on page 93). The data is always shifted from Master to
Slave on the Serial data Output line (SO), and from Slave to Master on the serial data Input line
(SI). Serial data is organized in 8-bit telegrams which are shifted with the most significant bit
(MSB) first.
T2IFR
T2IMR
MSB
T2RXB
T2TXB
SCLK
CLKT2
SI
SO
T2TXC
LSB
8-Bit Shift Register (SR)
SSI-Control
T2MRB
T2MDR(TXD)
T2MDR(RXD)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2BG100I | 40MX and 42MX FPGA Families |
| A42MX36-2BG100I | 40MX and 42MX FPGA Families |
| A42MX09-2PQ100 | 40MX and 42MX FPGA Families |
| A42MX16-2PQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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