參數(shù)資料
型號: A42MX16-2BG100I
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 100/120頁
文件大小: 854K
代理商: A42MX16-2BG100I
80
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.4.1
Timer1 Control Register – T1CR
Bit 7 - T1IE: Timer1 Interrupt Enable Bit
Writing T1IE to one enables an interval timer interrupt if the I bit in SREG is set. Writing T1IE to
zero disables the interrupt. The corresponding Interrupt Vector is executed when the T1F Flag,
located in T10IFR, is set.
Bit6 - Res: Reserved Bit
This bit is reserved bit at the ATA6289 and will always read as zero.
Bits 5..3 - T1CS2..0: Timer1 Clock Select Bits 2 - 0
The T1CS2, T1CS1, and T1CS0 bits select the input clock (CL1) of theTimer1, shown in Table
Bits 2..0 - T1PS2..0: Timer1 Prescaler Select Bits 2 - 0
The T1PS2, T1PS1, and T1PS0 bits determine the Timer1 prescaling clock output (CLK
T1). The
different prescaling values are shown in Table 3-35.
Bit
76
543210
T1IE
-
T1CS2
T1CS1
T1CS0
T1PS2
T1PS1
T1PS0
T1CR
Read/Write
R/W
R
R/W
Initial Value
00
000000
Table 3-34.
Timer1 Input Clock Select Bit Description
T1CS2
T1CS1
T1CS0
Input clock (CL1) of 12-bit prescaler
0
Disable(no clock source)
00
1
CLK
T0
01
0
CLK
I/O
01
1
CLT
10
0
T2I
10
1
T3I
11
0
Reserved
1
Reserved
Table 3-35.
Timer1 Prescaler Select Bit Description
T1PS2
T1PS1
T1PS0
Divider
000
CL1/ 2
001
CL1/ 4
010
CL1/ 8
0
1
CL1/ 16
1
0
CL1/ 32
101
CL1/ 256
110
CL1/ 1K
111
CL1/ 4K
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