參數(shù)資料
型號(hào)： A42MX16-1VQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： Power Transformer; Series:VPS; Power Rating:43VA; Mounting Type:Chassis; Current Rating:1.2 Series/2.4 Prllel A; External Depth:2.000"; External Height:2.688"; External Width:3.125"; Leaded Process Compatible:No
中文描述： 40MX和42MX FPGA系列
文件頁(yè)數(shù)： 7/120頁(yè)
文件大?。?/td> 854K
代理商： A42MX16-1VQ100
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104
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
OVF
Timer/counter overflow
CP
Capture event signal
CPR
Capture event reset signal
T3CPE
Timer/counter capture signal
3.13.7.3
Timer3 Control Register A – T3CRA
Bit 7 - T3E: Timer3 Enable Bit
This bit controls the Timer3 block. The T3E bit must be written to logic one to enable Timer3,
and if the T3E bit is written to logic zero, the Timer3 is disabled.
Bit 6 - T3TS: Timer3 Toggle with Start Bit
The T3TS bit must be written to logic one to toggle the modulator output of Timer3 when the
timer is enabled with T3E. If the T3TS bit is written to logic zero, the modulator output of Timer3
is not toggled with the timer enable.
Bits 5..3 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 2 - T3CR: Timer3 Counter Reset
The T3CR Bit resets the Counter3 asynchronously if this bit is set to logic 1.
Bit 1 - T3SCE: Timer3 Software Capture Enable Bit
The T32SCE bit must be written to logic one to generate a software capture event. The T3SCE
bit is cleared after the counter value is saved in the capture register. The Timer3 counter value is
readable via its capture register during run time.
Bit 0 - T3AC: Timer3 Alternate Compare Register Sequence Bit
The T3AC bit must be written to logic one to enable the compare registers alternate mode, and if
the T3AC bit is written to logic zero, the alternate mode is disabled.
3.13.7.4
Timer3 Control Register B – T3CRB
Bit 7 - Res: Reserved Bit
This bit is reserved bit at the ATA6289 and will always read as zero.
Bit 6 - T3CPRM: Timer3 CaPture Reset Mask Bit
The T3CPRM bit must be written to logic one to enable the counter reset if an internal/external
capture event occurs, and if the T3CPRM bit is written to logic zero, the counter reset is
disabled.
Bit
76
54
32
10
T3E
T3TS
-
T3CR
T3SCE
T3AC
T3CRA
Read/Write
R/W
R
R/W
Initial Value
00
Bit
76
5
4
3
2
1
0
-
T3CPRM T3CRMB T3SAMB T3CTMB T3CRMA T3SAMA T3CTMA T3CRB
Read/Write
R
R/W
Initial Value
00
0
相關(guān)PDF資料
PDF描述
A42MX24-1VQ100 Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:80VA; Mounting Type:Chassis; External Depth:2.313"; External Height:3.000"; External Width:2.500"; Leaded Process Compatible:Yes
A42MX36-1VQ100 XFRMR PWR 36.0VCT 3.6A QC .250
A42MX02-1VQ100A XFRMR PWR 36.0VCT 4.8A QC .250
A42MX04-1VQ100A XFRMR PWR 36.0VCT 0.7A QC .187
A42MX09-1VQ100A 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1VQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1VQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1VQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1VQ100I 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1VQ100M 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 100VQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP
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