參數(shù)資料
型號(hào)： A42MX16-1VQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： Power Transformer; Series:VPS; Power Rating:43VA; Mounting Type:Chassis; Current Rating:1.2 Series/2.4 Prllel A; External Depth:2.000"; External Height:2.688"; External Width:3.125"; Leaded Process Compatible:No
中文描述： 40MX和42MX FPGA系列
文件頁(yè)數(shù)： 112/120頁(yè)
文件大?。?/td> 854K
代理商： A42MX16-1VQ100
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91
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 2 - T2ICF: Timer2 Input Capture Flag Bit
This flag is set (one) and indicates that the Timer2/Counter2 value has been transferred to the
capture register (T2ICR) when a capture event from the T2ICP pin, an output clock of the Timer1
(CLK
T1) or a software capture event generated by the T2SCE bit occurs. T2ICF is automatically
cleared when the interrupt routine is executed. Alternatively, T2ICF can be cleared by writing a
logic one to this bit location. The T2ICF flag can be used to generate a Timer2 Capture interrupt
(see description of the T2CPIM bit in Section 3.13.5.13 “Timer2 Interrupt Mask Register –
Bit 1 - T2COF: Timer2 COmpare Flag Bit
This flag is set (one) if the Timer2/Counter2 value (T2CNT) matches with the Compare Register
value. The flag (T2COF) is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logic one to it. The T2COF flag can be used to generate a Timer2
Compare interrupt (see description of the T2CIM bit in Section 3.13.5.13 “Timer2 Interrupt Mask
Bit 0 - T2OFF: Timer2 OverFlow Flag Bit
This flag is set (one) if the Timer2/Counter2 overflow (OVF) occurs. An overflow (OVF) is gener-
ated if the “MAX”-value or the “TOP”-value of Timer2 is reached (see Table 3-36 on page 82).
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared
by writing a logical one to it. The T2OFF flag can be used to generate a Timer2 Overflow inter-
rupt (see description of the T2OIM bit in the following section).
3.13.5.13
Timer2 Interrupt Mask Register – T2IMR
Bits 7..6 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 5 - T2TCIM: Timer2 SSI Transmit Complete Interrupt Mask Bit
Writing this bit to one enables an interrupt on the T2TCF Flag. A Timer2 SSI transmit complete
interrupt (T2TXC) will be generated only if the T2TCIM bit is written to one, the Global Interrupt
Flag in SREG is written to one and the T2TCF bit in T2IFR is set.
Bit 4 - T2TXIM: Timer2 SSI Transmit Interrupt Mask Bit
Writing this bit to one enables an interrupt on the T2TXF Flag. A Timer2 SSI transmit buffer
empty interrupt T2TXB) will be generated only if the T2TXIM bit is written to one, the Global
Interrupt Flag in SREG is written to one and the T2TXF bit in T2IFR is set.
Bit 3 - T2RXIM: Timer2 SSI Receive Interrupt Mask Bit
Writing this bit to one enables an interrupt on the T2RXF Flag. A Timer2 SSI receive buffer full
interrupt (T2RXB) will be generated only if the T2RXIM bit is written to one, the Global Interrupt
Flag in SREG is written to one and the T2RXF bit in T2IFR is set.
Bit 2 - T2CPIM: Timer2 Capture Interrupt Mask Bit
Writing this bit to one enables an interrupt on the T2ICF Flag. A Timer2 capture interrupt
(T2CAP) will be generated only if the T2CPIM bit is written to one, the Global Interrupt Flag in
SREG is written to one and the T2ICF bit in T2IFR is set.
Bit
76
54
32
10
-
T2TCIM T2TXIM T2RXIM T2CPIM
T2CIM
T2OIM
T2IMR
Read/Write
R
R/W
Initial Value
00
相關(guān)PDF資料
PDF描述
A42MX24-1VQ100 Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:80VA; Mounting Type:Chassis; External Depth:2.313"; External Height:3.000"; External Width:2.500"; Leaded Process Compatible:Yes
A42MX36-1VQ100 XFRMR PWR 36.0VCT 3.6A QC .250
A42MX02-1VQ100A XFRMR PWR 36.0VCT 4.8A QC .250
A42MX04-1VQ100A XFRMR PWR 36.0VCT 0.7A QC .187
A42MX09-1VQ100A 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1VQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1VQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1VQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1VQ100I 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1VQ100M 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 100VQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP
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