參數(shù)資料
型號: 9EX21501AKLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 21501 SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64
封裝: ROHS COMPLIANT, PLASTIC, MLF-64
文件頁數(shù): 9/15頁
文件大小: 200K
代理商: 9EX21501AKLF
IDT
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
3
Datasheet
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1OE9#
IN
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
2
DIF_9
OUT
0.7V differential true clock output
DIF_9#
OUT
0.7V differential complement clock output
4
OE10#
IN
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
5
DIF_10
OUT
0.7V differential true clock output
6
DIF_10#
OUT
0.7V differential complement clock output
7
OE11#
IN
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
8
DIF_11
OUT
0.7V differential true clock output
9
DIF_11#
OUT
0.7V differential complement clock output
10
GND
PWR
Ground pin.
11
VDD
PWR
Power supply, nominal 3.3V
12
DIF_12
OUT
0.7V differential true clock output
13
DIF_12#
OUT
0.7V differential complement clock output
14
OE12#
IN
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
15
DIF_13
OUT
0.7V differential true clock output
16
DIF_13#
OUT
0.7V differential complement clock output
17
VDD
PWR
Power supply, nominal 3.3V
18
OE13_14#
IN
Active low input for enabling DIF pairs 13 and 14
1 = tri-state outputs, 0 = enable outputs
19
DIF_14
OUT
0.7V differential true clock output
20
DIF_14#
OUT
0.7V differential complement clock output
21
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value.
22
GNDA
PWR
Ground pin for the PLL core.
23
VDDA
PWR
3.3V power for the PLL core.
24
CLKA_IN
IN
True Input for differential reference clock.
25
CLKA_IN#
IN
Complement Input for differential reference clock.
26
GND
PWR
Ground pin.
27
CLKB_IN
IN
True Input for differential reference clock.
28
CLKB_IN#
IN
Complement Input for differential reference clock.
29
VDD
PWR
Power supply, nominal 3.3V
30
OE_01234#
IN
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
31
DIF_0
OUT
0.7V differential true clock output
32
DIF_0#
OUT
0.7V differential complement clock output
33
DIF_1
OUT
0.7V differential true clock output
34
DIF_1#
OUT
0.7V differential complement clock output
35
DIF_2
OUT
0.7V differential true clock output
36
DIF_2#
OUT
0.7V differential complement clock output
37
VDD
PWR
Power supply, nominal 3.3V
38
GND
PWR
Ground pin.
39
DIF_3
OUT
0.7V differential true clock output
40
DIF_3#
OUT
0.7V differential complement clock output
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