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參數(shù)資料
| 型號： | 9EX21501AKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 21501 SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-64 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 200K |
| 代理商： | 9EX21501AKLF |
IDT
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
4
Datasheet
Pin Description (continued)
41
DIF_4
OUT
0.7V differential true clock output
42
DIF_4#
OUT
0.7V differential complement clock output
43
OE5#
IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
44
DIF_5
OUT
0.7V differential true clock output
45
DIF_5#
OUT
0.7V differential complement clock output
46
OE6#
IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
47
DIF_6
OUT
0.7V differential true clock output
48
DIF_6#
OUT
0.7V differential complement clock output
49
VDD
PWR
Power supply, nominal 3.3V
50
OE7#
IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
51
DIF_7
OUT
0.7V differential true clock output
52
DIF_7#
OUT
0.7V differential complement clock output
53
100M_133M#
IN
Input to select operating frequency. See Frequency/Functionality Table for functionality of this pin.
54
HIBW_BYPM_LOBW#
IN
Trilevel input to select High BW, Bypass Mode or Low BW.
0 = Low BW Mode, Mid= Bypass Mode, 1 = High Bandwidth
55
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
56
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
57
SMB_A1
IN
SMBus address bit 1
58
SMB_A0
IN
SMBus address bit 0 (LSB)
59
SEL_A_B#
IN
Input to select differential input clock A or differential input clock B.
0 = Input B selected, 1 = Input A selected.
60
CKPWRGD/PD#
IN
Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling edge.
61
DIF_8
OUT
0.7V differential true clock output
62
DIF_8#
OUT
0.7V differential complement clock output
63
OE8#
IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
64
VDD
PWR
Power supply, nominal 3.3V
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9EX21501AKLFT | 功能描述:時鐘發(fā)生器及支持產品 PCIE BUFFER - GEN2. 15 OUTPUTS w/2:1 INP RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9EX21531AKLF | 功能描述:時鐘發(fā)生器及支持產品 PCIE BUFFER - GEN3, 15 OUTPUTS w/2:1 INP RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9EX21531AKLFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Single 64-Pin MLF T/R 制造商:Integrated Device Technology Inc 功能描述:64 MLF (LEAD FREE) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER - GEN3, 15 OUTPUTS w/2:1 INP |
| 9EX21801AKILF | 功能描述:時鐘發(fā)生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9EX21801AKILFT | 功能描述:時鐘發(fā)生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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