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參數(shù)資料
| 型號： | 97ULP877AHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-205, MO-225, FBGA-52 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 176K |
| 代理商： | 97ULP877AHLF-T |
12
ICS97ULP877A
7116—03/27/07
VDDQ
GND
VIA
CARD
VIA
CARD
BEAD
0603
4.7uF
1206
0.1uF
0603
2200pF
0603
PLL
AVDD
AGND
1
Ω
R1
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
AVDD Filtering
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PDF描述 |
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| 97ULP877BHLF-T | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97ULP877BHLF | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97ULP877BKLF | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 97ULP877BH | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97ULPA877AHLF-T | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 97ULP877BHLF | 功能描述:時鐘驅(qū)動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 97ULP877BHLFT | 功能描述:時鐘驅(qū)動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 97ULP877BKLF/W | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK DRVR SGL 95MHZ TO 410MHZ 40PIN VFQFPN - Tape and Reel |
| 97ULP878AH | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AH - Trays |
| 97ULP878AHLF | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AHLF - Trays |
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