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參數(shù)資料
| 型號： | 97ULP877BHLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | GREEN, PLASTIC, MO-205, MO-225, FBGA-52 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 252K |
| 代理商： | 97ULP877BHLF |
Integrated
Circuit
Systems, Inc.
ICS97ULP8 77B
0981B—03/15/05
Block Diagram
1.8V Low-Power Wide-Range Frequency Clock Driver
Pin Configuration
40-Pin MLF
Recommended Application:
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Switching Characteristics:
Period jitter: 40ps
Half-period jitter: 60ps
CYCLE - CYCLE jitter 40ps
OUTPUT - OUTPUT skew: 40ps
A
B
123456
C
D
E
F
G
H
J
K
52-Ball BGA
Top View
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
AV
DD
FB_INT
CLK_INT
CLK_INC
FB_INC
PLL
Powerdown
Control and
Test Logic
OE
LD* or OE
PLL bypass
LD*
LD*, OS or OE
OS
GND
10K-100k
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
VDDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
GND
CLKC7
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
OS
CLKT3
CLKC3
CLKC4
CLKT4
VDDQ
CLKT
9
CLKC
9
CLKC8
CLKT8
VDDQ
CLKC1
CLKT1
CLKT0
CLKC0
VDDQ
CLKC5
CLKT5
CLKT6
CLKC6
VDDQ
1
10
11
20
21
31
30
40
ICS97ULP877B
1234
5
6
A
CLKT1
CLKT0
CLKC0
CLKC5
CLKT5
CLKT6
B
CLKC1
GND
CLKC6
C
CLKC2
GND
NB
GND
CLKC7
D
CLKT2
VDDQ
OS
CLKT7
E
CLK_INT
VDDQ
NB
VDDQ
FB_INT
F
CLK_INC
VDDQ
NB
OE
FB_INC
G
AGND
VDDQ
FB_OUTC
H
AVDD
GND
NB
GND
FB_OUTT
J
CLKT3
GND
CLKT8
K
CLKC3
CLKC4
CLKT4
CLKT9
CLKC9
CLKC8
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| 97ULP877BKLF | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
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| 97ULPA877AHLF-T | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 980-1 | 0 MHz - 3000 MHz, 140 deg - RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
| 980-2 | 0 MHz - 3000 MHz, 340 deg - RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 97ULP877BHLFT | 功能描述:時鐘驅(qū)動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 97ULP877BKLF/W | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK DRVR SGL 95MHZ TO 410MHZ 40PIN VFQFPN - Tape and Reel |
| 97ULP878AH | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AH - Trays |
| 97ULP878AHLF | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AHLF - Trays |
| 97ULP878AHLFT | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AHLFT - Tape and Reel |
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