參數(shù)資料
型號: 97ULP877BHLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
封裝: GREEN, PLASTIC, MO-205, MO-225, FBGA-52
文件頁數(shù): 3/15頁
文件大?。?/td> 252K
代理商: 97ULP877BHLF
11
ICS97ULP8 77B
0981B—03/15/05
Figure 11. AVDD Filtering
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
相關(guān)PDF資料
PDF描述
97ULP877BKLF 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40
97ULP877BH 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
97ULPA877AHLF-T 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
980-1 0 MHz - 3000 MHz, 140 deg - RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER
980-2 0 MHz - 3000 MHz, 340 deg - RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER
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