參數(shù)資料
型號(hào): 97ULP877AHLF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
封裝: ROHS COMPLIANT, PLASTIC, MO-205, MO-225, FBGA-52
文件頁(yè)數(shù): 12/14頁(yè)
文件大?。?/td> 176K
代理商: 97ULP877AHLF-T
7
ICS97ULP877A
0981C—04/05/05
Notes:
1.
Switching characteristics guaranteed for application frequency range.
2.
Static phase offset shifted by design.
Switching Characteristics
1
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
(MHz)
MIN
TYP
MAX
UNITS
Output enable time
ten
OE to any output
4.73
8
ns
Output disable time
tdis
OE to any output
5.82
8
ns
160 to 270
-40
40
ps
271 to 410
-30
30
ps
160 to 270
-60
60
ps
271 to 410
-50
50
ps
Input Clock
1
2.5
4
v/ns
Output Enable (OE), (OS)
0.5
v/ns
Output clock slew rate
SLr1(o)
1.5
2.5
3
v/ns
tjit(cc+)
040
ps
tjit(cc-)
0-40
ps
160 to 270
-50
50
ps
271 to 410
-20
20
ps
Static Phase Offset
tSPO
2
271 to 410
-50
0
50
ps
t jit (per) + t ()dyn + t skew(o)
(su)
80
ps
t()dyn + tskew(o)
t (h)
60
ps
160 to 270
40
ps
271 to 410
30
ps
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency
deviation
0.00
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
t()dyn
Half-period jitter
tjit(hper)
Output to Output Skew
tskew
160 to 410
Period jitter
tjit (per)
Input slew rate
SLr1(i)
160 to 410
Cycle-to-cycle period jitter
Dynamic Phase Offset
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