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參數(shù)資料
| 型號： | 935271490512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 56/56頁 |
| 文件大?。?/td> | 715K |
| 代理商： | 935271490512 |
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
9 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
Type
Description
PLCC68 LQFP64 LQFP80
16/68
31
-
I
16/68 Interface type select (input with internal pull-up). This input
provides the 16 (Intel) or 68 (Motorola) bus interface type select. The
functions of IOR, IOW, INT A-INTD, and CSA-CSD are re-assigned
with the logical state of this pin. When this pin is a logic 1, the 16
mode interface (16C554) is selected. When this pin is a logic 0, the
68 mode interface (68C554) is selected. When this pin is a logic 0,
IOW is re-assigned to R/W, RESET is re-assigned to RESET, IOR is
not used, and INTA-INTD are connected in a wire-OR conguration.
The wire-OR outputs are connected internally to the open drain IRQ
signal output. This pin is not available on 64-pin packages which
operate in the 16 mode only.
A0
34
24
48
I
Address 0 select bit. Internal registers address selection in 16 and
68 modes.
A1
33
23
47
I
Address 1 select bit. Internal registers address selection in 16 and
68 modes.
A2
32
22
46
I
Address 2 select bit. Internal registers address selection in 16 and
68 modes.
A3, A4
20, 50
-
I
Address 3-4 select bits. When the 68 mode is selected, these pins
are used to address or select individual UARTs (providing CS is a
logic 0). In the 16 mode, these pins are re-assigned as chip selects,
see CSB and CSC. These pins are not available on 64-pin packages
which operate in the 16 mode only.
CDA, CDB,
CDC, CDD
9, 27,
43, 61
64, 18,
31, 49
19, 42,
59, 2
I
Carrier Detect (Active-LOW). These inputs are associated with
individual UART channels A through D. A logic 0 on this pin indicates
that a carrier has been detected by the modem for that channel.
CS
16
-
I
Chip Select (Active-LOW). In the 68 mode, this pin functions as a
multiple channel chip enable. In this case, all four UARTs (A-D) are
enabled when the CS pin is a logic 0. An individual UART channel is
selected by the data contents of address bits A3-A4. when the
16 mode is selected (68-pin devices), this pin functions as CSA (see
denition under CSA, CSB). This pin is not available on 64-pin
packages which operate in the 16 mode only.
CSA, CSB,
CSC, CSD
16, 20,
50, 54
7, 11,
38, 42
28, 33,
68, 73
I
Chip Select A, B, C, D (Active-LOW). This function is associated
with the 16 mode only, and for individual channels ‘A’ through ‘D’.
When in 16 mode, these pins enable data transfers between the user
CPU and the SC16C554/554D for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by providing a
logic 0 on the respective CSA-CSD pin. When the 68 mode is
selected, the functions of these pins are re-assigned. 68 mode
functions are described under their respective name/pin headings.
CTSA, CTSB,
CTSC, CTSD
11, 25,
45, 59
2, 16,
33, 47
23, 38,
63, 78
I
Clear to Send (Active-LOW). These inputs are associated with
individual UART channels A through D. A logic 0 on the CTS pin
indicates the modem or data set is ready to accept transmit data from
the SC16C554/554D. Status can be tested by reading MSR[4]. This
pin only affects the transmit or receive operations when Auto CTS
function is enabled via the Enhanced Feature Register EFR[7] for
hardware ow control operation.
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