參數(shù)資料
型號： 935271490512
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝： PLASTIC, MS-018, SOT-188-2, LCC-68
文件頁數(shù)： 4/56頁
文件大?。?/td> 715K
代理商： 935271490512
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
12 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
RXA, RXB,
RXC, RXD
7, 29,
41, 63
62, 20,
29, 51
17, 44,
57, 4
I
Receive data input RXA-RXD. These inputs are associated with
individual serial channel data to the SC16C554/554D. The RX signal
will be a logic 1 during reset, idle (no data), or when the transmitter is
disabled. During the local loop-back mode, the RX input pin is
disabled and TX data is connected to the UART RX input internally.
RXRDY
38
-
54
O
Receive Ready (Active-LOW). This function is associated with
68-pin package only. RXRDY contains the wire-ORed status of all
four receive channel FIFOs, RXRDYA-RXRDYD. A logic 0 indicates
receive data ready status, i.e., the RHR is full, or the FIFO has one or
more RX characters available for unloading. This pin goes to a
logic 1 when the FIFO/RHR is empty, or when there are no more
characters available in either the FIFO or RHR. Individual channel
RX status is read by examining individual internal registers via CS
and A0-A4 pin functions.
TXA, TXB,
TXC, TXD
17, 19,
51, 53
8, 10,
39, 41
29, 32,
69, 72
O
Transmit data A, B, C, D. These outputs are associated with
individual serial transmit channel data from the SC16C554/554D.
The TX signal will be a logic 1 during reset, idle (no data), or when
the transmitter is disabled. During the local loop-back mode, the TX
output pin is disabled and TX data is internally connected to the
UART RX input.
TXRDY
39
-
55
O
Transmit Ready (Active-LOW). This function is associated with the
68-pin package only. TXRDY contains the wire-ORed status of all
four transmit channel FIFOs, TXRDYA-TXRDYD. A logic 0 indicates a
buffer ready status, i.e., at least one location is empty and available in
one of the TX channels (A-D). This pin goes to a logic 1 when all four
channels have no more empty locations in the TX FIFO or THR.
Individual channel TX status can be read by examining individual
internal registers via CS and A0-A4 pin functions.
VCC
13, 30,
47, 64
4, 21,
35, 52
5, 25,
45, 65
I
Power supply inputs.
XTAL1
35
25
50
I
Crystal or external clock input. Functions as a crystal input or as
an external clock input. A crystal can be connected between this pin
and XTAL2 to form an internal oscillator circuit (see Figure 7).
Alternatively, an external clock can be connected to this pin to
provide custom data rates. (See Section 6.10 “Programmable baud
XTAL2
36
26
51
O
Output of the crystal oscillator or buffered clock. (See also
XTAL1.) Crystal oscillator output or buffered clock output.
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC68 LQFP64 LQFP80
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