參數(shù)資料
型號(hào)： 935271490512
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝： PLASTIC, MS-018, SOT-188-2, LCC-68
文件頁(yè)數(shù)： 14/56頁(yè)
文件大?。?/td> 715K
代理商： 935271490512
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
21 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Register descriptions
Table 8 details the assigned bit functions for the SC16C554/554D internal registers.
The assigned bit functions are more fully dened in Section 7.1 through Section 7.11.
[1]
The value shown represents the register’s initialized HEX value; X = n/a.
[2]
These registers are accessible only when LCR[7] = 0.
[3]
The Special Register set is accessible only when LCR[7] is set to a logic 1.
[4]
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.
Table 8:
SC16C554/554D internal registers
Shaded bits are only accessible when EFR[4] is set.
A2
A1
A0
Register Default[1] Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General Register Set[2]
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
IER
00
CTS
interrupt
RTS
interrupt
Xoff
interrupt
Sleep
mode
modem
status
interrupt
receive
line status
interrupt
transmit
holding
register
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
reserved reserved
DMA
mode
select
XMIT
FIFO reset
RCVR
FIFO
reset
FIFO
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
INT
priority
bit 4
INT
priority
bit 3
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
LCR
00
divisor
latch
enable
set
break
set parity even
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
1
0
MCR
00
0
IR
enable
0
loop back OP2,
INTx
enable
OP1
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
0
MSR
X0
CD
RI
DSR
CTS
CD
RI
DSR
CTS
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Special Register Set[3]
0
DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
DLM
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Enhanced Register Set[4]
0
1
0
EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable
IER[4-7],
ISR[4,5],
FCR[4,5],
MCR[5-7]
Cont-3
Tx, Rx
Control
Cont-2 Tx,
Rx Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
0
Xon-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
0
1
Xon-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
1
0
Xoff-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
Xoff-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
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