參數(shù)資料
型號： 935267488112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20
封裝： 7.50 MM, PLASTIC, SO-20
文件頁數(shù)： 33/69頁
文件大?。?/td> 352K
代理商： 935267488112
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
37
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 27
shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TFn. The count input is enabled to the Timer when TRn = 1 and
either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to
be controlled by external input INTn, to facilitate pulse width
measurements). TRn is a control bit in the Special Function Register
TCON (Figure 26). The GATE bit is in the TMOD register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits
of TLn. The upper 3 bits of TLn are indeterminate and should be
ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1. See
Figure 27. There are two different GATE bits, one for Timer 1
(TMOD.7) and one for Timer 0 (TMOD.3).
BIT
SYMBOL
FUNCTION
TCON.7
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
interrupt is processed, or by software.
TCON.6
TR1
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
TCON.5
TF0
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine, or by software.
TCON.4
TR0
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
TCON.3
IE1
Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
TCON.2
IT1
Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
TCON.1
IE0
Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
TCON.0
IT0
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
IT0
SU01172
IE0
IT1
IE1
TR0
TF0
TR1
TF1
0
1
2
3
4
5
6
7
TCON
Reset Value: 00h
Bit Addressable
Address: 88h
Figure 26. Timer/Counter Control Register (TCON)
SU01173
TLN
(5-BITS)
THN
(8-BITS)
OSC/6
OR
OSC/12
OVERFLOW
Tn PIN
TnOE
TOGGLE
CONTROL
C/T = 1
C/T = 0
Tn PIN
TRn
GATE
INTn PIN
INTERRUPT
TFn
Figure 27. Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
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