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參數(shù)資料
| 型號： | 935267488112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, SO-20 |
| 文件頁數(shù)： | 20/69頁 |
| 文件大?。?/td> | 352K |
| 代理商： | 935267488112 |
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Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
25
External Interrupt Inputs
The 87LPC768 has two individual interrupt inputs as well as the
Keyboard Interrupt function. The latter is described separately
elsewhere in this section. The two interrupt inputs are identical to
those present on the standard 80C51 microcontroller.
The external sources can be programmed to be level-activated or
transition-activated by setting or clearing bit IT1 or IT0 in Register
TCON. If ITn = 0, external interrupt n is triggered by a detected low
at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In
this mode if successive samples of the INTn pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEn in TCON
is set, causing an interrupt request.
Since the external interrupt pins are sampled once each machine
cycle, an input high or low should hold for at least 6 CPU Clocks to
ensure proper sampling. If the external interrupt is
transition-activated, the external source has to hold the request pin
high for at least one machine cycle, and then hold it low for at least
one machine cycle. This is to ensure that the transition is seen and
that interrupt request flag IEn is set. IEn is automatically cleared by
the CPU when the service routine is called.
If the external interrupt is level-activated, the external source must
hold the request active until the requested interrupt is actually
generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is
not necessary to clear the interrupt flag IEn when the interrupt is
level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the 87LPC768 is put into
Power Down or Idle mode, the interrupt will cause the processor to
wake up and resume operation. Refer to the section on Power
Reduction Modes for details.
SU01353
WAKEUP
(IF IN POWER
DOWN)
EA
(FROM IEN0
REGISTER)
INTERRUPT
TO CPU
IE0
EX0
IE1
EX1
BOD
EBO
KBF
EKB
CM2
EC2
WDT
EWD
ADC
EAD
TF0
ET0
TF1
ET1
RI + TI
ES
ATN
EI2
CM1
EC1
Figure 12. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources
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