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參數資料
| 型號： | 935267488112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, SO-20 |
| 文件頁數： | 22/69頁 |
| 文件大?。?/td> | 352K |
| 代理商： | 935267488112 |
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Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
27
Open Drain Output
Configuration
The open drain output configuration turns off all pull-ups and only
drives the pull-down transistor of the port driver when the port latch
contains a logic 0. To be used as a logic output, a port configured in
this manner must have an external pull-up, typically a resistor tied to
VDD. The pull-down for this mode is the same as for the
quasi-bidirectional mode.
The open drain port configuration is shown in Figure 14.
Push-Pull Output
Configuration
The push-pull output configuration has the same pull-down structure
as both the open drain and the quasi-bidirectional output modes, but
provides a continuous strong pull-up when the port latch contains a
logic 1. The push-pull mode may be used when more source current
is needed from a port output.
The push-pull port configuration is shown in Figure 15.
The three port pins that cannot be configured are P1.2, P1.3, and
P1.5. The port pins P1.2 and P1.3 are permanently configured as
open drain outputs. They may be used as inputs by writing ones to
their respective port latches. P1.5 may be used as a Schmitt trigger
input if the 87LPC768 has been configured for an internal reset and
is not using the external reset input function RST.
Additionally, port pins P2.0 and P2.1 are disabled for both input and
output if one of the crystal oscillator options is chosen. Those
options are described in the Oscillator section.
The value of port pins at reset is determined by the PRHI bit in the
UCFG1 register. Ports may be configured to reset high or low as
needed for the application. When port pins are driven high at reset,
they are in quasi-bidirectional mode and therefore do not source
large amounts of current.
Every output on the 87LPC768 may potentially be used as a 20 mA
sink LED drive output. However, there is a maximum total output
current for all ports which must not be exceeded.
All ports pins of the 87LPC768 have slew rate controlled outputs. This
is to limit noise generated by quickly switching output signals. The
slew rate is factory set to approximately 10 ns rise and fall times.
The bits in the P2M1 register that are not used to control
configuration of P2.1 and P2.0 are used for other purposes. These
bits can enable Schmitt trigger inputs on each I/O port, enable
toggle outputs from Timer 0 and Timer 1, and enable a clock output
if either the internal RC oscillator or external clock input is being
used. The last two functions are described in the Timer/Counters
and Oscillator sections respectively. The enable bits for all of these
functions are shown in Figure 16.
Each I/O port of the 87LPC768 may be selected to use TTL level
inputs or Schmitt inputs with hysteresis. A single configuration bit
determines this selection for the entire port. Port pins P1.2, P1.3,
and P1.5 always have a Schmitt trigger input.
SU01160
PORT
PIN
INPUT
DATA
PORT LATCH
DATA
N
Figure 14. Open Drain Output
SU01161
PORT
PIN
VDD
INPUT
DATA
PORT LATCH
DATA
N
P
Figure 15. Push-Pull Output
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