參數(shù)資料
型號(hào)： 935267488112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20
封裝： 7.50 MM, PLASTIC, SO-20
文件頁數(shù)： 24/69頁
文件大?。?/td> 352K
代理商： 935267488112
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
28
BIT
SYMBOL
FUNCTION
P2M1.7
P2S
When P2S = 1, this bit enables Schmitt trigger inputs on Port 2.
P2M1.6
P1S
When P1S = 1, this bit enables Schmitt trigger inputs on Port 1.
P2M1.5
P0S
When P0S = 1, this bit enables Schmitt trigger inputs on Port 0.
P2M1.4
ENCLK
When ENCLK is set and the 87LPC764 is configured to use the on-chip RC oscillator, a clock
output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details.
P2M1.3
ENT1
When set, the P.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore
one half of the Timer 1 overflow rate. Refer to the Timer/Counters section for details.
P2M1.2
ENT0
When set, the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore
one half of the Timer 0 overflow rate. Refer to the Timer/Counterssection for details.
P2M1.1, P2M1.0
—
These bits, along with the matching bits in the P2M2 register, control the output configuration of
P2.1 and P2.0 respectively, as shown in Table 4.
(P2M1.0)
SU01162
(P2M1.1)
ENT0
ENT1
ENCLK
P0S
P1S
P2S
0
1
2
3
4
5
6
7
P2M1
Reset Value: 00h
Not Bit Addressable
Address: A4h
Figure 16. Port 2 Mode Register 1 (P2M1)
Keyboard Interrupt (KBI)
The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the 87LPC768, as
shown in Figure 17. This interrupt may be used to wake up the CPU
from Idle or Power Down modes. This feature is particularly useful in
handheld, battery powered systems that need to carefully manage
power consumption yet also need to be convenient to use.
The 87LPC768 allows any or all pins of port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits in
the KBI register, as shown in Figure 18. The Keyboard Interrupt Flag
(KBF) in the AUXR1 register is set when any enabled pin is pulled
low while the KBI interrupt function is active. An interrupt will
generated if it has been enabled. Note that the KBF bit must be
cleared by software.
Due to human time scales and the mechanical delay associated with
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
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