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參數資料
| 型號： | 935267009118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數： | 5/27頁 |
| 文件大?。?/td> | 184K |
| 代理商： | 935267009118 |
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2000 Jul 11
13
Philips Semiconductors
Product specication
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
Notes
1. Asymmetrical drive on pin RFA or RFB; see Fig.3.
2. Bit PE needs to be set to logic 1 for a frequency higher than 2.3 GHz.
3. The drive level is expected with the crystal at series resonance with a series resistance of 50
. The value will be
different with another crystal.
4. To drive pin XTAL from the pin XT/COMP of another TSA5059, couple the signal through a capacitor of 1 nF
(to remove the DC level), in series with an 1.2 k
resistor; see Fig.5.
XT/COMP output (pin XT/COMP)
Vo(p-p)
AC output voltage (peak-to-peak value)
XCE = 1
400
mV
Input/output and output ports (pins P0, P1, P2 and P3)
IlO
port leakage current
port off; VO =VCC
10
A
VO(sat)
output port saturation voltage
port on; Isink =10mA
0.2
0.4
V
VIL
LOW-level input voltage
1.5
V
VIH
HIGH-level input voltage
3.0
V
ADC input (pin ADC)
ILIH
HIGH-level input leakage current
VADC =VCC
10
A
ILIL
LOW-level input leakage current
VADC =0V
10
A
Address selection (pin AS)
ILIH
HIGH-level input leakage current
VAS =VCC
1mA
ILIL
LOW-level input leakage current
VAS =0V
0.5
mA
SCL and SDA inputs (pins SCL and SDA)
VIL
LOW-level input voltage
1.5
V
VIH
HIGH-level input voltage
2.3
V
ILIH
HIGH-level input leakage current
VIH = 5.5 V
VCC = 5.5 V
10
A
VCC =0V
10
A
ILIL
LOW-level input leakage current
VIL =0V; VCC = 5.5 V
10
A
fSCL
SCL clock frequency
400
kHz
SDA output (pin SDA)
VO(ack)
output voltage during acknowledge
Isink =3mA
0.4
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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