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參數(shù)資料
| 型號： | 935267009118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 2/27頁 |
| 文件大?。?/td> | 184K |
| 代理商： | 935267009118 |
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2000 Jul 11
10
Philips Semiconductors
Product specication
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
XT/COMP frequency output
It is possible to output either the crystal or the comparison
frequency at this pin to be used in the application, for
example to drive a second PLL synthesizer, saving a
quartz crystal in the bill of material. To output fxtal, it is
necessary to set bit XCE to logic 1 and bit XCS to logic 0,
or bit XCE to logic 0 and bit XCS to logic 1 during a test
mode, while to output fcomp, it is necessary to set both
bits XCE and XCS to logic 1.
If the output signal at this pin is not used, it is
recommended to disable it, setting both bits XCE and XCS
to logic 0. Table 10 shows how this pin is programmed.
At power-on, the XT/COMP output is set, with the fxtal
signal selected.
Prescaler enable
The TSA5059 is able to work with the relation
fcomp = step size for an input frequency up to 2.3 GHz,
covering the complete satellite zero-IF frequency range.
For applications with an input frequency higher than
2.3 GHz, it is necessary to use the divide-by-two
prescaler.
The prescaler is selected by setting bit PE to logic 1 and
it is not in use if bit PE is set to logic 0.
For satellite zero-IF applications (frequency between
950 and 2 150 MHz), and especially if it is important to
reach a low phase noise on the controlled VCO, it is
recommended to set bit PE to logic 0, and not to use the
prescaler, allowing the comparison frequency to be equal
to the step size.
Test modes
It is possible to access the test modes by setting bit XCE
to logic 0 and bit XCS to logic 1. One specific test mode is
then selected using bits T2, T1 and T0, as described in
Table 10.
Table 10 XT/COMP and test mode selection; note 1
Notes
1. X = don’t care.
2. Status at Power-on reset.
XCE
XCS
T2
T1
T0
XT/COMP OUTPUT
TEST MODE
0
X
disabled
normal operation
1
0
XXX
fxtal
normal operation
1
XXX
fcomp
normal operation
01000
fxtal
test operation: charge pump sink;
status byte bit FL = 1
01001
fxtal
test operation: charge pump source;
status byte bit FL = 0
01010
fxtal
test operation: charge pump disabled;
status byte bit FL = 0
01011
fxtal
test operation: 1
2fDIV switched to Port P0
011
X
fxtal
test operation: tuning voltage (pin VT) is
off (high-impedance); note 2
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