參數(shù)資料
型號： 935267009118
廠商： NXP SEMICONDUCTORS
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16
封裝： 4.40 MM, PLASTIC, SSOP-16
文件頁數(shù)： 18/27頁
文件大?。?/td> 184K
代理商： 935267009118
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TSA5059
Information as of 2000-08-20
TSA5059; 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer
The TSA5059 is a single chip PLL frequency synthesizer designed for satellite tuning systems up to 2.7 GHz.
The RF preamplifier drives the 17-bit main divider enabling a step size equal to the comparison frequency, for an input frequency up to 2.3
GHz covering the complete satellite zero-IF frequency range. A fixed divide-by-two additional prescaler can be inserted between the
preamplifier and the main divider for a frequency between 2.3 and 2.7 GHz. In this case, the step size is twice the comparison frequency.
The comparison frequency is obtained from an on-chip crystal oscillator that can also be driven from an external source. Either the crystal
frequency or the comparison frequency can be switched to the XT/COMP output pin to drive the reference input of another synthesizer or
the clock input of a digital demodulation IC. Both divided and comparison frequency are compared into the fast phase detector which drives
the charge pump. The loop amplifier is also on-chip, including the high-voltage transistor to drive directly the 33 V tuning voltage, without
the need of an external transistor.
Control data is entered via the IC-bus; five serial bytes are required to address the device, select the main divider ratio, the reference
divider ratio, program the four output ports, set the charge pump current, select the prescaler by two, select the signal to switch to the
XT/COMP output pin and/or select a specific test mode. Three of the four output ports can also be used as input ports and a 5-level ADC is
provided. Digital information concerning the input ports and the ADC can be read out of the TSA5059 on the SDA line (one status byte)
during a READ operation. A flag is set when the loop is ‘in-lock’ and is read during a READ operation, as well as the Power-on reset flag.
The device has four programmable addresses, programmed by applying a specific voltage at pin AS, enabling the use of multiple
synthesizers in the same system.
l
Complete 2.7 GHz single chip system
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Optimized for low phase noise vSelectable divide-by-two prescaler
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Operation up to 2.3 GHz without divide-by-two prescaler (satellite zero-IF applications) and up to 2.7 GHz with divide-by-two
prescaler
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Selectable reference divider ratio
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相關(guān)PDF資料
PDF描述
935267010117 SPECIALTY ANALOG CIRCUIT, CQCC24
935268119112 SPECIALTY ANALOG CIRCUIT, PDSO16
935268119118 SPECIALTY ANALOG CIRCUIT, PDSO16
935268498557 PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24
935268498551 PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24
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