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參數(shù)資料
| 型號： | 935267009118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大?。?/td> | 184K |
| 代理商： | 935267009118 |
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2000 Jul 11
7
Philips Semiconductors
Product specication
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
Table 2
Explanation of Table 1
Address selection (see Table 3)
The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having
up to 4 synthesizers in one system. The relationship between MA1 and MA0 and the input voltage at pin AS is given
in Table 3.
Table 3
Address selection
Note
1. This address is selected by connecting a 15 k
resistor between pin AS and pin V
CC.
Status at Power-On Reset (POR)
At power-on or when the supply voltage drops below approximately 2.75 V, internal registers are set according to
Table 4.
Table 4
Status at Power-on reset; note 1
Notes
1. X = don’t care.
2. At Power-on reset, all output ports are in high-impedance state.
BIT
DESCRIPTION
MA1 and MA0
programmable address bits; see Table 3
A
acknowledge bit
N16 to N0
programmable main divider ratio control bits; N = N16
× 216 + N15 × 215 + ... + N1 × 21 +N0
PE
prescaler enable (prescaler by 2 is active when bit PE = 1)
R3 to R0
programmable reference divider ratio control bits; see Table 8
C1 and C0
charge pump current select bits; see Table 9
XCE
XT/COMP enable; XT/COMP output active when bit XCE = 1; see Table 10
XCS
XT/COMP select; signal select when bit XCE = 1, test mode enable when bit XCE = 0; see Table 10
T2, T1 and T0
test mode select when bit XCE = 0 and bit XCS = 1; see Table 10
P3, P2 and P1
Port P3, P2 and P1 output states
P0
Port P0 output state, except in test mode; see Table 10
MA1
MA0
VOLTAGE APPLIED TO PIN AS
0
0 to 0.1VCC
0
1
open-circuit
1
0
0.4VCC to 0.6VCC; note 1
1
0.9VCC to VCC
BYTE
DESCRIPTION
MSB
LSB
CONTROL BIT
1
address
1
1000
MA1
MA0
0
A
2
programmable divider
0
XXXXXX
X
A
3
programmable divider
X
XXXXXX
X
A
4
control data
1
XXXXXX
X
A
5
control data
0
1
X(2)
1(2)
X(2)
A
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