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參數(shù)資料
| 型號(hào)： | 935262451518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁(yè)數(shù)： | 134/144頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | 935262451518 |
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2000 Mar 15
9
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
Notes
1. In accordance with the
“IEEE1149.1” standard the pads TDI, TMS, TCK and TRST are input pads with an internal
pull-up transistor and TDO is a 3-state output pad.
2. Pin strapping is done by connecting the pin to supply via a 3.3 k
resistor. During the power-up reset sequence the
corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping
resistor is necessary (internal pull-down).
3. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave
address 40H/41H.
4. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.
5. For board design without boundary scan implementation connect the TRST pin to ground.
6. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
TEST4
78
O
do not connect; reserved for future extensions and for testing: scan output
TEST5
79
I
do not connect; reserved for future extensions and for testing: scan input
XTRI
80
I
X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH, XRV,
XDQ and XCLK), enable and active polarity is under software control (bits XPE
in subaddress 83H)
XPD7
81
I/O
expansion port data
XPD6
82
I/O
expansion port data
VDDD(ICO5)
83
P
internal digital core supply voltage 5 (+3.3 V)
XPD5 to XPD2
84 to 87
I/O
expansion port data
VSSD(ICO3)
88
P
internal digital core supply ground 3
XPD1
89
I/O
expansion port data
XPD0
90
I/O
expansion port data
XRV
91
I/O
vertical reference I/O expansion port
XRH
92
I/O
horizontal reference I/O expansion port
VDDD(ICO6)
93
P
internal digital core supply voltage 6 (+3.3 V)
XCLK
94
I/O
clock I/O expansion port
XDQ
95
I/O
data qualier I/O expansion port
XRDY
96
O
task ag or ready signal from scaler, controlled by XRQT
TRST
97
I
test reset input (active LOW), for boundary scan test (with internal pull-up);
notes 5 and 6
TCK
98
I
test clock for boundary scan test; note 1
TMS
99
I
test mode select input for boundary scan test or scan test; note 1
VSSD(EP4)
100
P
external digital pad supply ground 4
SYMBOL
PIN
TYPE
DESCRIPTION
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