參數(shù)資料
型號： 935262451518
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100
文件頁數(shù)： 117/144頁
文件大?。?/td> 592K
代理商： 935262451518
2000 Mar 15
74
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
LEdc(d)
DC differential linearity
error
0.7
LSB
LEdc(i)
DC integral linearity error
1
LSB
Digital inputs
VIL(SCL,SDA)
LOW-level input voltage
pins SDA and SCL
0.5
+0.3VDDD
V
VIH(SCL,SDA)
HIGH-level input voltage
pins SDA and SCL
0.7VDDD
VDDD + 0.5
V
VIL(XTALI)
LOW-level CMOS input
voltage pin XTALI
0.3
+0.8
V
VIH(XTALI)
HIGH-level CMOS input
voltage pin XTALI
2.0
VDDD + 0.3
V
VIL(n)
LOW-level input voltage all
other inputs
0.3
+0.8
V
VIH(n)
HIGH-level input voltage
all other inputs
2.0
5.5
V
ILI
input leakage current
1
A
ILI/O
I/O leakage current
10
A
Ci
input capacitance
I/O at high impedance
8pF
Digital outputs; note 1
VOL(SDA)
LOW-level output voltage
pin SDA
SDA at 3 mA sink current
0.4
V
VOL(clk)
LOW-level output voltage
for clocks
0.5
+0.6
V
VOH(clk)
HIGH-level output voltage
for clocks
2.4
VDDD + 0.5
V
VOL
LOW-level output voltage
all other digital outputs
0
0.4
V
VOH
HIGH-level output voltage
all other digital outputs
2.4
VDDD + 0.5
V
Clock output timing (LLC and LLC2); note 2
CL
output load capacitance
15
50
pF
Tcy
cycle time
pin LLC
35
39
ns
pin LLC2
70
78
ns
δ
duty factors for tLLCH/tLLC
and tLLC2H/tLLC2
CL =40pF
40
60
%
tr
rise time LLC and LLC2
0.2 V to VDDD 0.2 V
5ns
tf
fall time LLC and LLC2
VDDD 0.2 V to 0.2 V
5ns
td(LLC-LLC2)
delay time between LLC
and LLC2 output
measured at 1.5 V;
CL =25pF
4
+8
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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