參數(shù)資料
型號： 935262451518
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100
文件頁數(shù)： 112/144頁
文件大小： 592K
代理商： 935262451518
2000 Mar 15
7
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
7
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
VDDD(EP1)
1
P
external digital pad supply voltage 1 (+3.3 V)
TDO
2
O
test data output for boundary scan test; note 1
TDI
3
I
test data input for boundary scan test; note 1
XTOUT
4
O
crystal oscillator output signal; auxiliary signal
VSS(XTAL)
5
P
ground for crystal oscillator
XTALO
6
O
24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock
input of XTALI is used
XTALI
7
I
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of
external oscillator with TTL compatible square wave clock signal
VDD(XTAL)
8
P
supply voltage for crystal oscillator
VSSA2
9
P
ground for analog inputs AI2n
AI24
10
I
analog input 24
VDDA2
11
P
analog supply voltage for analog inputs AI2n (+3.3 V)
AI23
12
I
analog input 23
AI2D
13
I
differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21)
AI22
14
I
analog input 22
VSSA1
15
P
ground for analog inputs AI1n
AI21
16
I
analog input 21
VDDA1
17
P
analog supply voltage for analog inputs AI1n (+3.3 V)
AI12
18
I
analog input 12
AI1D
19
I
differential input for ADC channel 1 (pins AI12 and AI11)
AI11
20
I
analog input 11
AGND
21
P
analog ground connection
AOUT
22
O
do not connect; analog test output
VDDA0
23
P
analog supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC)
VSSA0
24
P
ground for internal clock generation circuit
VDDD(EP2)
25
P
external digital pad supply voltage 2 (+3.3 V)
VSSD(EP1)
26
P
external digital pad supply ground 1
CE
27
I
chip enable or reset input (with internal pull-up)
LLC
28
O
line-locked system clock output (27 MHz nominal)
LLC2
29
O
line-locked 1
2 clock output (13.5 MHz nominal)
RES
30
O
reset output (active LOW)
SCL
31
I(/O)
serial clock input (I2C-bus) with inactive output path
SDA
32
I/O
serial data input/output (I2C-bus)
VDDD(ICO1)
33
P
internal digital core supply voltage 1 (+3.3 V)
RTS0
34
O
real-time status or sync information, controlled by subaddresses 11H and 12H;
see Section 15.2.18, 15.2.19 and 15.2.20
RTS1
35
O
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