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參數(shù)資料
| 型號(hào)： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁數(shù)： | 59/120頁 |
| 文件大?。?/td> | 447K |
| 代理商： | 91C94 |
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43
I/O SPACE - BANK0
OFFSET
A
NAME
MEMORY CONFIGURATION
REGISTER
TYPE
Lower Byte - READ/WRITE
Upper Byte - READ ONLY
SYMBOL
MCR
HIGH
BYTE
MEMORY SIZE MULTIPLIER M
0
1
0
1
LOW
BYTE
MEMORY RESERVED FOR TRANSMIT (in bytes x 256 x M)
0
MEMORY
RESERVED
FOR
TRANSMIT
-
Programming this value allows the host CPU to
reserve memory to be used later for transmit,
limiting the amount of memory that receive
packets can use up.
When
programmed
for
zero,
the
memory
allocation between transmit and receive is
completely dynamic.
When programmed for a non-zero value, the
allocation is dynamic if the free memory
exceeds the programmed value, while receive
allocation requests are denied if the free
memory is less or equal to the programmed
value.
This register defaults to zero upon reset. It is not
affected by the RESET MMU command.
The value written to the MCR is a reserved
memory
space
IN
ADDITION
TO
ANY
MEMORY CURRENTLY IN USE. If the memory
allocated for transmit plus the reserved space
for transmit is required to be constant (rather
than grow with transmit allocations) the CPU
should update the value of this register after
allocating or releasing memory.
The contents of MIR as well as the low byte of
MCR are specified in 256 x M bytes.
The
multiplier M is determined by bits 11,10,and 9
as follows. Bits 11,10 and 9 are read only bits
used by the software driver to transparently run
on different controllers of the LAN9000 family:
DEVICE
BIT 11
BIT 10
BIT 9
M
MAX MEMORY SIZE
LAN91C100
0
1
0
2
256 x 256 x 2=128k
LAN91C90
0
1
256 x 256 x 1 =64k
FUTURE
0
1
4
256k
" "
1
0
8
512k
" "
1
0
1
16
1M
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