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參數(shù)資料
| 型號： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁數(shù)： | 34/120頁 |
| 文件大小： | 447K |
| 代理商： | 91C94 |
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20
FUNCTIONAL DESCRIPTION
Except for the bus interface, the functional
behavior
of
the
LAN91C94
after
initial
configuration is identical for ISA and PCMCIA
modes.
The LAN91C94 includes an arbitrated shared
memory of 4608 bytes, accessed by the CPU
through two sequential access regions of 2
kbytes each, as well as a register area.
The MMU unit allocates RAM memory to be
used for transmit and receive packets, using
256 byte pages.
The arbitration is transparent to the CPU in
every sense. There is no speed penalty for ISA
type of machines due to arbitration. There are
no
restrictions
on
what
locations
can
be
accessed at any time. RAM accesses as well as
MMU requests are arbitrated.
The RAM is accessed by mapping it into I/O
space for sequential access.
Except for the
RAM accesses and the MMU request/release
commands, I/O accesses are not arbitrated.
The I/O space is 16 bits wide. Provisions for 8
bit systems are handled by the bus interface.
In the system memory space, up to 64 kbytes
are decoded by the LAN91C94 as expansion
ROM. The ROM expansion area is 8 bits wide.
Device configuration is done using a serial
EEPROM, with support for modifications to the
EEPROM at installation time. A Flash ROM is
supported for PCMCIA attribute memory.
The CSMA/CD core implements the 802.3 MAC
layer
protocol.
It
has
two
independent
interfaces, the data path and the control path.
Both interfaces are 16 bits wide.
The control path provides a set of registers used
to configure and control the block.
These
registers are accessible by the CPU through the
LAN91C94 I/O space.
The data path is of
sequential access nature and typically works in
one direction at any given time.
An internal
DMA type of interface connects the data path to
the device RAM through the arbiter and MMU.
The CSMA/CD data path interface is not
accessible to the host CPU.
The internal DMA interface can arbitrate for
RAM access and request memory from the
MMU when necessary.
An
encoder/decoder
block
interfaces
the
CSMA/CD block on the serial side. The encoder
will do the Manchester encoding of the transmit
data at 10 Mbit/s, while the decoder will recover
the receive clock, and decode received data.
Carrier and Collision detection signals are also
handled by this block and relayed to the
CSMA/CD block.
The encoder/decoder block can interface the
network through the AUI interface pairs, or it can
be programmed to use the internal 10BASE-T
transceiver and connect to a twisted pair
network.
The twisted pair interface takes care of the
medium dependent signaling for 10BASE-T type
of networks. It is responsible for line interface
(with external pulse transformers and pre-
distortion resistors), collision detection as well
as the link integrity test function.
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