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參數(shù)資料
| 型號(hào)： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁(yè)數(shù)： | 105/120頁(yè) |
| 文件大小： | 447K |
| 代理商： | 91C94 |
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85
Transmit Functions
Manchester Encoding
The PHY encodes the transmit data received
from the MAC.
The encoded data is directed
internally to the selected output driver for
transmission over the twisted-pair network or
the AUI cable. Data transmission and encoding
is initiated by the Transmit Enable input, TXE,
going low.
Transmit Drivers
The encoded transmit data passes through to
the transmit driver pair, TPETXP(N), and its
complement, TPETXDP(N). Each output of the
transmit driver pair has a source resistance of
10 ohms maximum and a current rating of 25
mA maximum.
The degree of predistortion is
determined by the termination resistors; the
equivalent resistance should be 100 ohms.
Jabber Function
This integrated function prevents the DTE from
locking into a continuous transmit state.
In
10BASE-T mode, if transmission continues
beyond the specified time limit, the jabber
function
inhibits
further
transmission
and
asserts the collision indicator nCOLL. The limits
for jabber transmission are 20 to 15 ms in
10BASE-T mode. In the AUI mode, the jabber
function
is
performed
by
the
external
transceiver.
SQE Function
In the 10BASE-T mode, the PHY supports the
signal quality error (SQE) function. At the end
of a transmission, the PHY asserts the nCOLL
signal for 10+/-5 bit times beginning 0.6 to
1.6ms after the last positive transition of a
transmitted frame. In the AUI mode, the SQE
function
is
performed
by
the
external
transceiver.
Receive Functions
Receive Drivers
Differential signals received off the twisted-pair
network or AUI cable are directed to the internal
clock recovery circuit prior to being decoded for
the MAC.
Manchester Decoder and Clock Recovery
The
PHY
performs
timing
recovery
and
Manchester decoding of incoming differential
signals in 10BASE-T or AUI modes, with its
built-in phase-lock loop (PLL).
The decoded
(NRZ) data, RXD, and the recovered clock,
RXCLK,
becomes
available
to
the
MAC,
typically within 9 bit times (5 for AUI) after the
assertion of nCRS. The receive clock, RXCLK,
is phase-locked to the transmit clock in the
absence of a received signal (idle).
Squelch Function
The integrated smart squelch circuit employs a
combination
of
amplitude
and
timing
measurements to determine the validity of data
received off the network. It prevents noise at the
differential inputs from falsely triggering the
decoder in the absence of valid data or link test
pulses. Signal levels below 300mV (180mV for
AUI) or pulse widths less than 15ns at the
differential inputs are rejected.
Signals above
585mV (300mV for AUI) and pulse widths
greater than 30ns will be accepted. When using
the extended cable mode with 10BASE-T media
which extends beyond the standard limit of 100
meters, the squelch level can optionally be set
to reject signals below 180mV and accept
signals above 300mV.
If the input signal
exceeds the squelch requirements, the carrier
sense output, nCRS, is asserted.
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