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參數(shù)資料
| 型號(hào)： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁(yè)數(shù)： | 103/120頁(yè) |
| 文件大小： | 447K |
| 代理商： | 91C94 |
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83
CSMA BLOCK
The CSMA/CD block is first interfaced via its
control registers in order to define its operational
configuration. From then on, the DMA interface
between the CSMA/CD block and memory is
used to transfer data to and from its data path
interface.
For transmit, the CSMA/CD block will be asked
to transmit frames as soon as they are ready in
memory. It will continue transmissions until any
of the following transmit error occurs:
a) 16 collisions on same frame
b) Late collision
c) Lost Carrier sense and MON_CSN set.
d) Transmit Under run.
e) SQET error and STP_SQET set.
In that case TXENA will be cleared and the CPU
should restart the transmission by setting it
again. If a transmission is successful, TXENA
stays set and the CSMA/CD is provided by the
DMA
block
with
the
next
packet
to
be
transmitted.
For receive, the CPU sets RXEN as a way of
starting the CSMA/CD block receive process.
The CSMA/CD block will send data after
address filtering through the data path to the
DMA block. Data is transferred into memory as
it is received, and the final check on data
acceptance is the CRC checking done by the
CSMA/CD block. In any case, the DMA takes
care of requesting/releasing memory for receive
packets, as well as generating the byte count.
The receive status word is provided by the
CSMA/CD block and written in the first location
of the receive structure by the DMA block.
If
configured for storing CRC in memory, the
CSMA/CD unit will transfer the CRC bytes
through the DMA interface, and then will be
treated like regular data bytes.
Note that the receive status word of any packet
is available only through memory and is not
readable through any other register. In order to
let the CPU know about receive overruns, the
RX_OVRN bit is latched into the Interrupt Status
Register, which is readable by the CPU at any
time.
The
address
filtering
is
done
inside
the
CSMA/CD block. A packet will be received if the
destination address is broadcast, or if it is
addressed to the individual address of the
LAN91C94, or if it is a multicast address and
ALMUL bit is set, or if it is a multicast address
matching one of the multicast table entries. If
the PRMS bit is set, all packets are received.
The CSMA/CD block is a full duplex machine,
and when working in full duplex mode, the
CSMA/CD block will be simultaneously using its
data path transmit and receive interfaces.
Statistical counters are kept by the CSMA/CD
block, and are readable through the appropriate
register. The counters are four bits each, and
can generate an interrupt when reaching their
maximum values.
Software can use that
interrupt to update statistics in memory, or it can
keep the counter interrupt disabled, while relying
on the transmit interrupt routine reading the
counters.
Given
that
the
counters
can
increment only once per transmit, this technique
is a good complement for the single interrupt
per sequence strategy.
The interface between the CSMA/CD block and
memory is word oriented.
Two bi-directional
FIFOs make the data path interface.
Whenever a normal collision occurs (less than
16 retries), the CSMA/CD will trigger the backoff
logic and will indicate the DMA logic of the
collision. The DMA is responsible for restarting
the data transfer into the CSMA/CD block
regardless of whether the collision happened on
the preamble or not.
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