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參數(shù)資料
| 型號： | 87LPC762 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low power, low price, low pin count 20 pin microcontroller with 2 kbyte OTP |
| 中文描述： | 低功耗，低價格，低管腳數(shù)的2字節(jié)OTP 20引腳微控制器 |
| 文件頁數(shù)： | 30/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | 87LPC762 |
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Philips Semiconductors
Preliminary data
87LPC762
Low power, low price, low pin count (20 pin)
microcontroller with 2 kbyte OTP
2001 Oct 26
27
Low Voltage EPROM Operation
The EPROM array contains some analog circuits that are not
required when V
DD
is less than 4 V, but are required for a V
DD
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with V
DD
less than 4 V.
Reset
The 87LPC762 has an integrated power-on reset circuit which
always provides a reset when power is initially applied to the device.
It is recommended to use the internal reset whenever possible to
save external components and to be able to use pin P1.5 as a
general-purpose input pin.
The 87LPC762 can additionally be configured to use P1.5 as an
external active-low reset pin RST by programming the RPD bit in the
User Configuration Register UCFG1 to 0. The internal reset is still
active on power-up of the device. While the signal on the RST pin is
low, the 87LPC762 is held in reset until the signal goes high.
The watchdog timer on the LPC762 can act as an oscillator fail
detect because it uses an independent, fully on-chip oscillator.
UCFG1 is described in the System Configuration Bytes section of
this datasheet.
SU01226
87LPC762
P1.5
Pin is used as
digital input pin
Internal power-on
Reset active
UCFG1.RPD = 1 (default)
87LPC762
RST
Pin is used as
active-low reset pin
Internal power-on
Reset active
UCFG1.RPD = 0
Figure 20. Using pin P1.5 as general purpose input pin or as low-active reset pin
SU01170
CHIP RESET
CPU
CLOCK
Q
RESET
TIMING
RPD (UCFG1.6)
WDT
MODULE
SOFTWARE RESET
SRST (AUXR1.3)
POWER MONITOR
RESET
RST/V
PP
PIN
WDTE (UCFG1.7)
S
R
Figure 21. Block Diagram Showing Reset Sources
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