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參數(shù)資料
| 型號： | 87LPC762 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low power, low price, low pin count 20 pin microcontroller with 2 kbyte OTP |
| 中文描述： | 低功耗，低價格，低管腳數(shù)的2字節(jié)OTP 20引腳微控制器 |
| 文件頁數(shù)： | 16/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | 87LPC762 |
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Philips Semiconductors
Preliminary data
87LPC762
Low power, low price, low pin count (20 pin)
microcontroller with 2 kbyte OTP
2001 Oct 26
13
BIT
I2CON.7
“
I2CON.6
“
SYMBOL
RDAT
CXA
ATN
IDLE
FUNCTION
Read: the most recently received data bit.
Write: clears the transmit active flag.
Read: ATN = 1 if any of the flags DRDY, ARL, STR, or STP = 1.
Write: in the I
2
C slave mode, writing a 1 to this bit causes the I
2
C hardware to ignore the bus until it
is needed again.
Read: Data Ready flag, set when there is a rising edge on SCL.
Write: writing a 1 to this bit clears the DRDY flag.
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
Write: writing a 1 to this bit clears the CARL flag.
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STR flag.
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STP flag.
Read: indicates whether this device is currently as bus master.
Write: writing a 1 to this bit causes a repeated start condition to be generated.
Read: undefined.
Write: writing a 1 to this bit causes a stop condition to be generated.
I2CON.5
“
I2CON.4
“
I2CON.3
“
I2CON.2
“
I2CON.1
“
I2CON.0
“
DRDY
CDR
ARL
CARL
STR
CSTR
STP
CSTP
MASTER
XSTR
—
XSTP
—
SU01155
MASTER
STP
STR
ARL
DRDY
ATN
RDAT
0
1
2
3
4
5
6
7
I2CON
Reset Value: 81h
Bit Addressable
1
Address: D8h
XSTP
XSTR
CSTP
CSTR
CARL
CDR
IDLE
CXA
READ
WRITE
Figure 6. I
2
C Control Register (I2CON)
BIT
I2DAT.7
SYMBOL
RDAT
FUNCTION
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
Unused.
“
XDAT
I2DAT.6–0
–
—
SU01156
—
—
—
—
—
—
RDAT
0
1
2
3
4
5
6
7
I2DAT
Reset Value: xxh
Not Bit Addressable
Address: D9h
—
—
—
—
—
—
—
XDAT
READ
WRITE
Figure 7. I
2
C Data Register (I2DAT)
Checking ATN and DRDY
When a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I
2
C will not go on to the next bit. If a program detects
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR,
and STP.
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